A 256-Mb SDRAM using a register-controlled digital DLL. - Atsushi Hatakeyama; Hirohiko Mochizuki; Tadao Aikawa; Masato Takita; Yuki Ishii; Hironobu Tsuboi; Shin-ya Fujioka; Shusaku Yamaguchi; Makoto Koga; Yuji Serizawa; Koichi Nishimura; Kuninori Kawabata; et al. (IEEE J. Solid State Circuits, 1997)

500-Mb/s nonprecharged data bus for high-speed DRAM's. - Miyoshi Saito; Junji Ogawa; Hirotaka Tamura; Shigetoshi Wakayama; Hisakatsu Araki; Tsz-Shing Cheung; Kohtaroh Gotoh; Tadao Aikawa; Takaaki Suzuki; Masao Taguchi; Takeshi Imamura (IEEE J. Solid State Circuits, 1998)