Distributed Communicating Media-A Multitrack Bus-Capable of Concurrent Data Exchanging. - Makoto Hasegawa; Tadao Nakamura; Yoshiharu Shigei (ISCA, 1981)

A Language Processor of an Intelligent Link System. - Tadao Nakamura; Hiroaki Kobayashi; Jun Miyajima; Noboru Endo; Yoshiharu Shigei (ICC (2), 1984)

An Analysis of the Receiving Behaviour of a Window Flow Control Mechanism in Packet Switching Networks. - Kuninobu Tanno; Tadao Nakamura; Risaburo Sato (ICC (3), 1984)

Evaluating the parallelism of the feed-forward machine and algorithms of the machine. - Masayuki Tomisawa; Hidekazu Yamada; Tadao Nakamura; Yoshiharu Shigei (Syst. Comput. Jpn., 1985)

A Hierarchical General-Purpose Pipeline System. - Noboru Endo; Tadao Nakamura; Yoshiharu Shigei (Syst. Comput. Jpn., 1986)

Matrix representation of programs within an intelligent link. - Jun Miyajima; Noboru Endo; Tadao Nakamura; Yoshiharu Shigei (Syst. Comput. Jpn., 1986)

Signal processing on a parallel pipeline-structured data-flow computer system. - Nobuyuki Oba; Tadao Nakamura; Yoshiharu Shigei (Syst. Comput. Jpn., 1986)

Characteristics of a programmable logic unit. - Takahiko Murayama; Hidekazu Yamada; Tadao Nakamura; Yoshiharu Shigei; Yoshio Yoshioka (Syst. Comput. Jpn., 1987)

Performance evaluation of a computer using programmable logic units. - Takahiko Murayama; Hidekazu Yamada; Tadao Nakamura; Yoshiharu Shigei; Yoshio Yoshioka (Syst. Comput. Jpn., 1987)

An adaptive routing method for computer networks by electric-circuit modeling. - Nobuyuki Oba; Tadao Nakamura; Yoshiharu Shigei (Syst. Comput. Jpn., 1987)

Realization of computers using programmable logic units. - Hidekazu Yamada; Tadao Nakamura; Yoshiharu Shigei; Takahiko Murayama; Yoshio Yoshioka (Syst. Comput. Jpn., 1987)

Parallel processing of an object space for image synthesis using ray tracing. - Hiroaki Kobayashi; Tadao Nakamura; Yoshiharu Shigei (Vis. Comput., 1987)

Load balancing strategies for a parallel ray-tracing system based on constant subdivision. - Hiroaki Kobayashi; Satoshi Nishimura; Hideyuki Kubota; Tadao Nakamura; Yoshiharu Shigei (Vis. Comput., 1988)

Semiparallel execution of compiled Lisp programs. - Masa-Aki Fukase; Tadao Nakamura (COMPSAC, 1991)

Parallel Processing and Hardware Support of Symbols. - Masa-Aki Fukase; Tadao Nakamura (ICTAI, 1993)

An Adaptive Network Routing Method by Electrical-Circuit Modeling. - Nobuyuki Oba; Hiroaki Kobayashi; Tadao Nakamura (INFOCOM, 1993)

Software pipelining for Jetpipeline architecture. - Masayuki Katahira; Takehito Sasaki; Hong Shen; Hiroaki Kobayashi; Tadao Nakamura (ISPAN, 1994)

The Convergence of Asynchronous Monotone Newton Iterations on Distributed Computer. - Jie Hu 010; Tadao Nakamura; Lei Li 045 (PP, 1995)

A Divide-and-inner Product Parallel Algorithm for Polynomial Evaluation. - Jie Hu 010; Lei Li 045; Tadao Nakamura (Parallel Algorithms Appl., 1995)

The Convergence of Asynchronous Iterations for the Fixed Point of a Splitting Operator. - Lei Li 045; Tadao Nakamura (Parallel Algorithms Appl., 1995)

A Hierarchical Parallel Processing System for the Multipass-Rendering Method. - Hiroaki Kobayashi; Hitoshi Yamauchi; Yuichiro Toh; Tadao Nakamura (IPPS, 1996)

A construction of back-propagation neural networks including time delay elements (BPD). - Masaaki Nishi; Junji Furuya; Tadao Nakamura (Syst. Comput. Jpn., 1996)

A Simple Parallel Algorithm for Polynomial Evaluation. - Lei Li 045; Jie Hu 010; Tadao Nakamura (SIAM J. Sci. Comput., 1996)

Parallel processing of the shear-warp factorization with the binary-swap method on a distributed-memory multiprocessor system. - Kentaro Sano; Hiroyuki Kitajima; Hiroaki Kobayashi; Tadao Nakamura (PRS, 1997)

Asynchronous Monotone Newton Iterative Method on Distributed Computers. - Jie Hu 010; Tadao Nakamura; Lei Li 045 (Parallel Algorithms Appl., 1997)

Convergence, Complexity and Simulation of Monotone Asynchronous Iterative Method for Computing Fixed Point on a Distributed Computer. - Jie Hu 010; Tadao Nakamura; Lei Li 045 (Parallel Algorithms Appl., 1997)

Decoupled modified-bit cache. - Masafumi Takahashi; Nobuyuki Oba; Hiroaki Kobayashi; Tadao Nakamura (Syst. Comput. Jpn., 1997)

Automated Design of Wave Pipelined Multiport Register Files. - Kouji Takano; Takehito Sasaki; Nobuyuki Oba; Hiroaki Kobayashi; Tadao Nakamura (ASP-DAC, 1998)

A self-organizing network system forming memory from nonstationary probability distributions. - Taira Nakajima; Hiroyuki Takizawa; Hiroaki Kobayashi; Tadao Nakamura (IJCNN, 1999)

Introducing cool chips. - Tadao Nakamura (IEEE Micro, 1999)

A scheduling method for instruction-level parallel processing of vectorand scalar instructions. - Takuya Nakaike; Takehito Sasaki; Masayuki Katahira; Hiroaki Kobayashi; Tadao Nakamura (Syst. Comput. Jpn., 1999)

Time stamp invalidation of TLB-unified cache and its performance evaluation. - Ken-ichi Suzuki; Nobuyuki Oba; Shigenori Shimizu; Hiroaki Kobayashi; Tadao Nakamura (Syst. Comput. Jpn., 1999)

Reconfigurable synchronized dataflow processor. - Hiroshi Sasaki; Hitoshi Maruyama; Hideaki Tsukioka; Nobuyoshi Shoji; Hiroaki Kobayashi; Tadao Nakamura (ASP-DAC, 2000)

Fast parallel algorithms for vandermonde determinants. - Lei Li 045; Tadao Nakamura (Int. J. Comput. Math., 2000)

Cool Chips III. - Tadao Nakamura (IEEE Micro, 2000)

3DCGiRAM: An Intelligent Memory Architecture for Photo-Realistic Image Synthesis. - Hiroaki Kobayashi; Ken-ichi Suzuki; Kentaro Sano; Yoshiyuki Kaeriyama; Yasumasa Saida; Nobuyuki Oba; Tadao Nakamura (ICCD, 2001)

An Active Network for Improving Performance of Traffic Flow over Conventional ATM Service. - Emad Rashid; Takashi Araki; Tadao Nakamura (ICN (2), 2001)

Variable-Length Coding based on Bent Sequences for W.ireless Advertising. - Emad Rashid; Yoshio Yoshioka; Takashi Araki; Tadao Nakamura (ISCC, 2001)

Scaling Up Of Wave Pipelines. - Masa-Aki Fukase; Ryusuke Egawa; Tomoaki Sato; Tadao Nakamura (VLSI Design, 2001)

Moderating traffic flow over conventional ATM service. - Tomoyuki Nagase; Takashi Araki; Yoshio Yoshioka; Tadao Nakamura (ISCC, 2002)

Hardware Support for Concurrent Execution of Loops Containing Loop-carried Data Dependences. - C. D. Lima; Kentaro Sano; Tadao Nakamura (IASTED PDCS, 2002)

Parallel Algorithm for the Law-of-the-Jungle Learning to the Fast Design of Optimal Codebooks. - Kentaro Sano; Shintaro Momose; Hiroyuki Takizawa; Taira Nakajima; C. D. Lima; Hiroaki Kobayashi; Tadao Nakamura (IASTED PDCS, 2002)

Exploiting Loop-Level Parallelism with the Shift Architecture. - Clecio Donizete Lima; Tadao Nakamura (SBAC-PAD, 2002)

Toward Architecting and Designing Novel Computers. - Tadao Nakamura (Asia-Pacific Computer Systems Architecture Conference, 2003)

Parallel competitive learning algorithm for fast codebook design on partitioned space. - Shintaro Momose; Kentaro Sano; Ken-ichi Suzuki; Tadao Nakamura (CLUSTER, 2004)

A Systolic Memory Architecture for Fast Codebook Design based on MMPDCL Algorithm. - Kentaro Sano; Chiaki Takagi; Ryusuke Egawa; Ken-ichi Suzuki; Tadao Nakamura (ITCC (1), 2004)

Differential coding scheme for efficient parallel image composition on a PC cluster system. - Kentaro Sano; Yusuke Kobayashi 005; Tadao Nakamura (Parallel Comput., 2004)

Efficient parallel processing of competitive learning algorithms. - Kentaro Sano; Shintaro Momose; Hiroyuki Takizawa; Hiroaki Kobayashi; Tadao Nakamura (Parallel Comput., 2004)

An Operand Status Based Instruction Steering Scheme for Clustered Architectures. - Yukinori Sato; Ken-ichi Suzuki; Tadao Nakamura (CDES, 2005)

Cooperation of Neighboring PEs in Clustered Architectures. - Yukinori Sato; Ken-ichi Suzuki; Tadao Nakamura (SBAC-PAD, 2005)

A Competitive Learning Algorithm with Controlling Maximum Distortion. - Takeshi Miura; Kentaro Sano; Ken-ichi Suzuki; Tadao Nakamura (J. Adv. Comput. Intell. Intell. Informatics, 2005)

Ray Tracing Hardware System Using Plane-Sphere Intersections. - Yoshiyuki Kaeriyama; Daichi Zaitsu; Kazuhiko Komatsu; Ken-ichi Suzuki; Tadao Nakamura; Nobuyuki Ohba (FPL, 2006)

Power Estimation of Partitioned Register Files in a Clustered Architecture with Performance Evaluation. - Yukinori Sato; Ken-ichi Suzuki; Tadao Nakamura (IEICE Trans. Inf. Syst., 2007)

Guest Editors' Introduction: ICFPT 2007. - Hideharu Amano; Tadao Nakamura (ACM Trans. Reconfigurable Technol. Syst., 2009)

Development of ultra-thinning technology for logic and memory heterogeneous stack applications. - Nobuhide Maeda; Young-Suk Kim; Y. Hikosaka; T. Eshita; Hideki Kitada; K. Fujimoto; Yoriko Mizushima; K. Suzuki; Tadao Nakamura; Akihito Kawai; Kazuhisa Arai; Takayuki Ohba (3DIC, 2011)

On-the-fly detection of precise loop nests across procedures on a dynamic binary translation system. - Yukinori Sato; Yasushi Inoguchi; Tadao Nakamura (Conf. Computing Frontiers, 2011)

Whole program data dependence profiling to unveil parallel regions in the dynamic execution. - Yukinori Sato; Yasushi Inoguchi; Tadao Nakamura (IISWC, 2012)

Evaluating reconfigurable dataflow computing using the Himeno benchmark. - Yukinori Sato; Yasushi Inoguchi; Wayne Luk; Tadao Nakamura (ReConFig, 2012)

Influence of wafer thinning process on backside damage in 3D integration. - Tadao Nakamura; Yoriko Mizushima; Hideki Kitada; Young-Suk Kim; Nobuhide Maeda; Shoichi Kodama; Ryuichi Sugie; Hiroshi Hashimoto; Akihito Kawai; Kazuhisa Arai; Akira Uedono; Takayuki Ohba (3DIC, 2013)

An additional condition for Bell experiments for accepting local realistic theories. - Koji Nagata; Tadao Nakamura (Quantum Inf. Process., 2013)

A low power NoC router using the marching memory through type. - Ryota Yasudo; Takahiro Kagami; Hideharu Amano; Yasunobu Nakase; Masashi Watanabe; Tsukasa Oishi; Toru Shimizu; Tadao Nakamura (COOL Chips, 2014)

Design of a low power NoC router using Marching Memory Through type. - Ryota Yasudo; Takahiro Kagami; Hideharu Amano; Yasunobu Nakase; Masashi Watanabe; Tsukasa Oishi; Toru Shimizu; Tadao Nakamura (NOCS, 2014)

Identifying Program Loop Nesting Structures during Execution of Machine Code. - Yukinori Sato; Yasushi Inoguchi; Tadao Nakamura (IEICE Trans. Inf. Syst., 2014)

On-Chip Decentralized Routers with Balanced Pipelines for Avoiding Interconnect Bottleneck. - Ryota Yasudo; Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano; Tadao Nakamura (NOCS, 2015)

Message from the advisory committee chair. - Tadao Nakamura (COOL Chips, 2016)

Panel discussions: "Cool chips for the next decade". - Hideharu Amano; Tadao Nakamura; Hiroaki Kobayashi; Hironori Kasahara; Yoshiaki Hagiwara; Jeffrey L. Burns; David Brash (COOL Chips, 2017)

Scalable Networks-on-Chip with Elastic Links Demarcated by Decentralized Routers. - Ryota Yasudo; Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano; Tadao Nakamura (IEEE Trans. Computers, 2017)

An Introduction to Marching Memory (MM). - Tadao Nakamura (3DIC, 2019)

Nonparametric Regression Quantum Neural Networks. - Do Ngoc Diep; Koji Nagata; Tadao Nakamura (CoRR, 2020)

Quantum cryptography based on an algorithm for determining simultaneously all the mappings of a Boolean function. - Koji Nagata; Renata Wong; Do Ngoc Diep; Tadao Nakamura (IACR Cryptol. ePrint Arch., 2021)

Computational complexity in high-dimensional quantum computing. - Koji Nagata; Do Ngoc Diep; Tadao Nakamura (Quantum Mach. Intell., 2022)

Two symmetric measurements may cause an unforeseen effect. - Koji Nagata; Do Ngoc Diep; Tadao Nakamura (Quantum Inf. Process., 2023)