Phase-adjustable error detection flip-flops with 2-stage hold driven optimization and slack based grouping scheme for dynamic voltage scaling. - Masanori Kurimoto; Hiroaki Suzuki; Rei Akiyama; Tadao Yamanaka; Haruyuki Ohkuma; Hidehiro Takata; Hirofumi Shinohara (DAC, 2008)

Post-silicon programmed body-biasing platform suppressing device variability in 45 nm CMOS technology. - Hiroaki Suzuki; Masanori Kurimoto; Tadao Yamanaka; Hidehiro Takata; Hiroshi Makino; Hirofumi Shinohara (ISLPED, 2008)

Phase-adjustable error detection flip-flops with 2-stage hold-driven optimization, slack-based grouping scheme and slack distribution control for dynamic voltage scaling. - Masanori Kurimoto; Hiroaki Suzuki; Rei Akiyama; Tadao Yamanaka; Haruyuki Ohkuma; Hidehiro Takata; Hirofumi Shinohara (ACM Trans. Design Autom. Electr. Syst., 2010)