Implementing Intelligence on Silicon Using Neuron-Like Functional MOS Transistors. - Tadashi Shibata; Koji Kotani; Takeo Yamashita; Hiroshi Ishii 005; Hideo Kosaka; Tadahiro Ohmi (NIPS, 1993)

Neuron-MOS Temporal Winner Search Hardware for Fully-Parallel Data Processing. - Tadashi Shibata; Tsutomu Nakai; Tatsuo Morimoto; Ryu Kaihara; Takeo Yamashita; Tadahiro Ohmi (NIPS, 1995)

A neuron-MOS neural network using self-learning-compatible synapse circuits. - Tadashi Shibata; Hideo Kosaka; Hiroshi Ishii 005; Tadahiro Ohmi (IEEE J. Solid State Circuits, 1995)

Implementing Intelligence in Silicon Integrated Circuits Using Neuron-Like High-Functionality Transistors. - Tadashi Shibata; Tadahiro Ohmi (J. Robotics Mechatronics, 1996)

Functional-Device-Based VLSI for Intelligent Electronic Systems. - Tadashi Shibata (ISMVL, 1998)

Neuron-MOS continuous-time winner-take-all circuit for intelligent data processing. - Tatsuo Morimoto; Tadashi Shibata; Tadahiro Ohmi (KES (3), 1998)

Right brain computing hardware: a psychological brain model on silicon. - Tadashi Shibata (KES (3), 1998)

CMOS charge-transfer preamplifier for offset-fluctuation cancellation in low-power A/D converters. - Koji Kotani; Tadashi Shibata; Tadahiro Ohmi (IEEE J. Solid State Circuits, 1998)

A neuron-MOS parallel associator for high-speed CDMA matched filter. - Atsuhiko Okada; Tadashi Shibata (ISCAS (2), 1999)

A fully parallel vector-quantization processor for real-time motion-picture compression. - Akira Nakada; Tadashi Shibata; Masahiro Konda; Tatsuo Morimoto; Tadahiro Ohmi (IEEE J. Solid State Circuits, 1999)

Association hardware for intelligent electronic systems. - Tadahiro Ohmi; Tadashi Shibata; Koji Kotani; Tsutomu Nakai; Akira Nakada; Ning Mei Yu; Masahiro Konda; Tatsuo Morimoto; Yuichiro Yamashita (Syst. Comput. Jpn., 1999)

A hardware-friendly soft-computing algorithm for image recognition. - Masakazu Yagi; Masayoshi Adachi; Tadashi Shibata (EUSIPCO, 2000)

High-precision analog EEPROM with real-time write monitoring. - Keng Hoong Wee; Toshiyuki Nozawa; Takemi Yonezawa; Yuichiro Yamashita; Tadashi Shibata; Tadahiro Ohmi (ISCAS (1), 2001)

An analog similarity evaluation circuit featuring variable functional forms. - Toshihiko Yamasaki; Tadashi Shibata (ISCAS (3), 2001)

A fast self-convergent flash-memory programming scheme for MV and analog data storage. - Toshihiko Yamasaki; Atsushi Suzuki; Daisuke Kobayashi; Tadashi Shibata (ISCAS (4), 2001)

Human-perception-like image recognition system based on the Associative Processor architecture. - Masakazu Yagi; Tadashi Shibata; Kenji Takada (EUSIPCO, 2002)

A human-perception-like image recognition system based on PAP vector representation with multi resolution concept. - Masakazu Yagi; Tadashi Shibata (ICASSP, 2002)

A motion-based analog VLSI saliency detector using quasi-two-dimensional hardware algorithm. - Hiroe Kimura; Tadashi Shibata (ISCAS (3), 2002)

A zone-programmed EEPROM with real-time write monitoring for analog data storage. - Keng Hoong Wee; T. Yonezawa; Toshiyuki Nozawa; Tadashi Shibata; Tadahiro Ohmi (ISCAS (4), 2002)

An associative-processor-based mixed signal system for robust grayscale image recognition. - Masakazu Yagi; Tadashi Shibata (ISCAS (5), 2002)

Low-power CDMA analog matched filters based on floating-gate technology. - Toshihiko Yamasaki; Teruyasu Taguchi; Tadashi Shibata (ISCAS (5), 2002)

Intelligent Internet Search Applications Based on VLSI Associative Processors. - Huaiyu Xu; Yoshio Mita; Tadashi Shibata (SAINT, 2002)

Intelligent Signal Processing Based on a Psychologically-Inspired VLSI Brain Model. - Tadashi Shibata (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

An analog image processing LSI employing scanning line-parallel processing. - Teruyasu Taguchi; Makoto Ogawa; Tadashi Shibata (ESSCIRC, 2003)

Robust cephalometric landmark identification using support vector machines. - Shantanu Chakrabartty; Masakazu Yagi; Tadashi Shibata; Gert Cauwenberghs (ICASSP (2), 2003)

Speaker and text independent language identification using predictive error histogram vectors. - Qian-Rong Gu; Tadashi Shibata (ICASSP (1), 2003)

A Mixed-Signal VLSI for Real-Time Generation of Edge-Based Image Vectors. - Masakazu Yagi; Hideo Yamasaki; Tadashi Shibata (NIPS, 2003)

A Robust Medical Image Recognition System Employing Edge-Based Feature Vector Representation. - Masakazu Yagi; Tadashi Shibata; Chihiro Tanikawa; Kenji Takada (SCIA, 2003)

A fully integrated 0.13-μm CMOS mixed-signal SoC for DVD player applications. - Koji Okamoto; Takashi Morie; Akira Yamamoto; Kouichi Nagano; Koji Sushihara; Hiroyuki Nakahira; Ryusuke Horibe; Kazutoshi Aida; Toshihiko Takahashi; Minoru Ochiai; Akinobu Soneda; Toru Kakiage; et al. (IEEE J. Solid State Circuits, 2003)

Guest editorial - Special issue on neural networks hardware implementations. - Bernabé Linares-Barranco; Andreas G. Andreou; Giacomo Indiveri; Tadashi Shibata (IEEE Trans. Neural Networks, 2003)

An image representation algorithm compatible with neural-associative-processor-based hardware recognition systems. - Masakazu Yagi; Tadashi Shibata (IEEE Trans. Neural Networks, 2003)

Analog soft-pattern-matching classifier using floating-gate MOS technology. - Toshihiko Yamasaki; Tadashi Shibata (IEEE Trans. Neural Networks, 2003)

A delay-encoding-logic array processor for dynamic programming matching. - Makoto Ogawa; Tadashi Shibata (ESSCIRC, 2004)

An edge-based face detection algorithm robust against illumination, focus, and scale variations. - Yasufumi Suzuki; Tadashi Shibata (EUSIPCO, 2004)

Multiple-clue face detection algorithm using edge-based feature vectors. - Yasufumi Suzuki; Tadashi Shibata (ICASSP (5), 2004)

Quasi-parallel multi-path detection architecture using floating-gate-MOS-based CDMA matched filters. - Tomoyuki Nakayama; Toshihiko Yamasaki; Tadashi Shibata (ISCAS (1), 2004)

A bump-circuit-based motion detector using projected-activity histograms. - Masayuki Umejima; Toshihiko Yamasaki; Tadashi Shibata (ISCAS (1), 2004)

A real-time VLSI median filter employing two-dimensional bit-propagating architecture. - Hideo Yamasaki; Tadashi Shibata (ISCAS (2), 2004)

A high-speed median filter VLSI using floating-gate-MOS-based low-power majority voting circuits. - Hideo Yamasaki; Tadashi Shibata (ESSCIRC, 2005)

A new distance measure employing element-significance factors for robust image classification. - Kunio Kawahara; Tadashi Shibata (EUSIPCO, 2005)

Multiple-resolution edge-based feature representations for robust face segmentation and verification. - Yasufumi Suzuki; Tadashi Shibata (EUSIPCO, 2005)

A low-power switched-current CDMA matched filter employing MOS-linear matching cell and output A/D converter. - Tomoyuki Nakayama; Toshihiko Yamasaki; Tadashi Shibata (ISCAS (6), 2005)

A computational digital-pixel-sensor VLSI featuring block-readout architecture for pixel-parallel rank-order filtering. - Benjamas Tongprasit; Kiyoto Ito; Tadashi Shibata (ISCAS (3), 2005)

An Analog Visual Pre-Processing Processor Employing Cyclic Line Access in Only-Nearest-Neighbor-Interconnects Architecture. - Yusuke Nakashita; Yoshio Mita; Tadashi Shibata (NIPS, 2005)

A delay-encoding-logic array processor for dynamic-programming matching of data sequences. - Makoto Ogawa; Tadashi Shibata (IEEE J. Solid State Circuits, 2005)

A low-power and compact CDMA matched filter based on switched-current technology. - Toshihiko Yamasaki; Tomoyuki Nakayama; Tadashi Shibata (IEEE J. Solid State Circuits, 2005)

Multi-view face detection and pose estimation employing edge-based feature vectors. - Daisuke Moriya; Yasufumi Suzuki; Tadashi Shibata; Masakazu Yagi; Kenji Takada (EUSIPCO, 2006)

Illumination-invariant face identification using edge-based feature vectors in pseudo-2D Hidden Markov Models. - Yasufumi Suzuki; Tadashi Shibata (EUSIPCO, 2006)

A Vlsi-Implementation-Friendly EGO-Motion Detection Algorithm Based on Edge-Histogram Matching. - Jia Hao 007; Tadashi Shibata (ICASSP (2), 2006)

A time-domain gradient-detection architecture for VLSI analog motion sensors. - Kiyoto Ito; Tadashi Shibata (ISCAS, 2006)

Power-balanced reconfigurable floating-gate-MOS logic circuit for tamper resistant VLSI. - Benjamas Tongprasit; Tadashi Shibata (ISCAS, 2006)

A speed adaptive ego-motion detection system using EDGE-histograms produced by variable graduation method. - Jia Hao 007; Tadashi Shibata (EUSIPCO, 2007)

Validating directional edge-based image feature representations in face recognition by spatial correlation-based clustering. - Yasufumi Suzuki; Tadashi Shibata (EUSIPCO, 2007)

A Feature-Based Optical Flow Processor Architecture Featuring Single-Motion-Vector/Cycle Generation. - Kazuhide Fujita; Kiyoto Ito; Tadashi Shibata (SoC, 2007)

Mixed-Signal Focal-Plane Image Processor Employing Tme-domaiin Computation Architecture. - Kiyoto Ito; Tadashi Shibata (SoC, 2007)

A Real-Time Learning Processor Based on K-means Algorithm with Automatic Seeds Generation. - Hirotsugu Shikano; Kiyoto Ito; Kazuhide Fujita; Tadashi Shibata (SoC, 2007)

An Intelligent Action Control System Based on Extended Vector Annotated Logic Program and its Hardware Implementation. - Kazumi Nakamatsu; Yoshio Mita; Tadashi Shibata (Intell. Autom. Soft Comput., 2007)

A Low-Power Floating-Gate-MOS-Based CDMA Matched Filter Featuring Coupling Capacitor Disconnection. - Toshihiko Yamasaki; Tadashi Shibata (IEEE J. Solid State Circuits, 2007)

A Real-Time Image-Feature-Extraction and Vector-Generation VLSI Employing Arrayed-Shift-Register Architecture. - Hideo Yamasaki; Tadashi Shibata (IEEE J. Solid State Circuits, 2007)

Blind image compression history determination using dynamic thresholding. - Robert Grou-Szabo; Tadashi Shibata (ICASSP, 2008)

Spatiotemporal projection of motion field sequence for generating feature vectors in gesture perception. - Hitoshi Hayakawa; Tadashi Shibata (ISCAS, 2008)

An analog self-similitude edge-filtering processor for multiple-resolution image perception. - Norihiro Takahashi; Kazuhide Fujita; Tadashi Shibata (ISCAS, 2008)

Special Section on Advanced Processors Based on Novel Concepts in Computation. - Tadashi Shibata (IEICE Trans. Electron., 2008)

Bio-inspired devices, circuits and systems. - Tadashi Shibata (ESSCIRC, 2009)

A real-time image recognition system using a global directional-edge-feature extraction VLSI processor. - Hongbo Zhu; Tadashi Shibata (ESSCIRC, 2009)

A Non-subtraction Configuration of Self-similitude Architecture for Multiple-Resolution Edge-Filtering CMOS Image Sensor. - Norihiro Takahashi; Tadashi Shibata (ICANN (1), 2009)

Normalized scoring of Hidden Markov Models by on-line learning and its application to gesture-sequence perception. - Mio Nishiyama; Tadashi Shibata (ICIP, 2009)

A Single-motion-vector/Cycle-generation Optical Flow Processor Employing Directional-edge Histogram Matching. - Kazuhide Fujita; Kiyoto Ito; Tadashi Shibata (ISCAS, 2009)

Block-matching-based CMOS Optical Flow Sensor using Only-nearest-neighbor Computation. - Yudai Fukuoka; Tadashi Shibata (ISCAS, 2009)

A Real-time Image Feature Vector Generator Employing Functional Cache Memory for Edge Flags. - Takuki Nakagawa; Tadashi Shibata (ISCAS, 2009)

A low-power switched-current CDMA matched filter employing MOS linear matching cell with on-chip A/D converter. - Toshihiko Yamasaki; Tomoyuki Nakayama; Tadashi Shibata (Integr., 2009)

A Computational Digital Pixel Sensor Featuring Block-Readout Architecture for On-Chip Image Processing. - Kiyoto Ito; Benjamas Tongprasit; Tadashi Shibata (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

A Pixel-Parallel Self-Similitude Processing for Multiple-Resolution Edge-Filtering Analog Image Sensors. - Norihiro Takahashi; Kazuhide Fujita; Tadashi Shibata (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

A Low-Power Associative Processor with the R-th Nearest-Match Hamming-Distance Search Engine Employing Time-Domain Techniques. - Trong Tu Bui; Tadashi Shibata (DELTA, 2010)

A self-learning multiple-class classifier using multi-dimensional quasi-Gaussian analog circuits. - Zhuoli Sun; Kyunghee Kang; Tadashi Shibata (ISCAS, 2010)

A row-parallel cyclic-line-access edge detection CMOS image sensor employing global thresholding operation. - Norihiro Takahashi; Tadashi Shibata (ISCAS, 2010)

Directional-edge-based object tracking employing on-line learning and regeneration of multiple candidate locations. - Hongbo Zhu; Pushe Zhao; Tadashi Shibata (ISCAS, 2010)

Block-matching-based motion field generation utilizing directional edge displacement. - Hitoshi Hayakawa; Tadashi Shibata (Comput. Electr. Eng., 2010)

An Ego-Motion Detection System Employing Directional-Edge-Based Motion Field Representations. - Jia Hao 007; Tadashi Shibata (IEICE Trans. Inf. Syst., 2010)

A Neuron-MOS-Based VLSI Implementation of Pulse-Coupled Neural Networks for Image Feature Generation. - Jun Chen; Tadashi Shibata (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

An On-Chip-Trainable Gaussian-Kernel Analog Support Vector Machine. - Kyunghee Kang; Tadashi Shibata (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

Spatio-temporal motion field descriptors for the hierarchical action recognition system. - Ruihan Bao; Tadashi Shibata (ICSPCS, 2011)

A dominant-noise discrimination system for images corrupted by content-independent noises without a priori references. - Robert Grou-Szabo; Tadashi Shibata (ICSPCS, 2011)

Critical Boundary Vector Concept in Nearest Neighbor Classifiers using k-Means Centers for Efficient Template Reduction. - Wenjun Xia; Tadashi Shibata (IJCCI (NCTA), 2011)

A vertical-MOSFET-based digital core circuit for high-speed low-power vector matching. - Yitao Ma; Tetsuo Endoh; Tadashi Shibata (ISOCC, 2011)

Unsupervised object extraction by contour delineation and texture-based discrimination. - Litian Sun; Tadashi Shibata (EUSIPCO, 2012)

A Hierarchical Action Recognition System Applying Fisher Discrimination Dictionary Learning via Sparse Representation. - Ruihan Bao; Tadashi Shibata (ICAISC (1), 2012)

Real-Time On-Line-Learning Support Vector Machine Based on a Fully-Parallel Analog VLSI Processor. - Renyuan Zhang; Tadashi Shibata (ICAISC (2), 2012)

Real-Time Object Tracking Algorithm Employing On-Line Support Vector Machine and Multiple Candidate Regeneration. - Pushe Zhao; Renyuan Zhang; Tadashi Shibata (ICAISC (1), 2012)

Scene image recognition based on the sequence of local image vectors represented by oriented edges. - Shigetaka Morikawa; Tadashi Shibata (ICASSP, 2012)

Translation-invariant motion perception for multiple objects using grid partitioning representation. - Mio Nishiyama; Tadashi Shibata (ICSPCS, 2012)

Self-adaptive quasi-Gaussian circuits for analog on-chip-trainable multi-class classifiers. - Wenjun Xia; Tadashi Shibata (ISCAS, 2012)

A real-time motion-feature-extraction image processor employing digital-pixel-sensor-based parallel architecture. - Hongbo Zhu; Tadashi Shibata (ISCAS, 2012)

An MTJ-based nonvolatile associative memory architecture with intelligent power-saving scheme for high-speed low-power recognition applications. - Yitao Ma; Tadashi Shibata; Tetsuo Endoh (ISCAS, 2013)

A VLSI DBSCAN processor composed as an array of micro agents having self-growing interconnects. - Atsushi Shimada 002; Hongbo Zhu; Tadashi Shibata (ISCAS, 2013)

A multiple-candidate-regeneration-based object tracking system with enhanced learning capability by nearest neighbor classifier. - Pushe Zhao; Hongbo Zhu; Tadashi Shibata (ISCAS, 2013)

A hardware friendly algorithm for action recognition using spatio-temporal motion-field patches. - Ruihan Bao; Tadashi Shibata (Neurocomputing, 2013)

A Directional-Edge-Based Real-Time Object Tracking System Employing Multiple Candidate-Location Generation. - Pushe Zhao; Hongbo Zhu; He Li; Tadashi Shibata (IEEE Trans. Circuits Syst. Video Technol., 2013)

A single-chip 600-fps real-time action recognition system employing a hardware friendly algorithm. - Zuoxun Hou; Hongbo Zhu; Nanning Zheng 001; Tadashi Shibata (ISCAS, 2014)

Unsupervised Object Extraction by Contour Delineation and Texture Discrimination Based on Oriented Edge Features. - Litian Sun; Tadashi Shibata (IEEE Trans. Circuits Syst. Video Technol., 2014)

A Real-Time Motion-Feature-Extraction VLSI Employing Digital-Pixel-Sensor-Based Parallel Architecture. - Hongbo Zhu; Tadashi Shibata (IEEE Trans. Circuits Syst. Video Technol., 2014)

A Nearest Neighbor Classifier Employing Critical Boundary Vectors for Efficient On-Chip Template Reduction. - Wenjun Xia; Yoshio Mita; Tadashi Shibata (IEEE Trans. Neural Networks Learn. Syst., 2016)