A 5.8-ns 256-Kb BiCMOS TTL SRAM with T-Shaped bit line architecture. - Toru Shiomi; Tomohisa Wada; Shigeki Ohbayashi; Atsushi Ohba; Hiroki Honda; Yoshiyuki Ishigaki; Shiro Hine; Kenji Anami; Kimio Suzuki; Tadashi Sumi (IEEE J. Solid State Circuits, 1993)

A half-pel precision MPEG2 motion-estimation processor with concurrent three-vector search. - Kazuya Ishihara; Shinichi Masuda; Shin-ichi Hattori; Hirofumi Nishikawa; Yoshihide Ajioka; Tsuyoshi Yamada; Hiroyuki Amishiro; Shin-ichi Uramoto; Masahiko Yoshimoto; Tadashi Sumi (IEEE J. Solid State Circuits, 1995)

A 286 MHz 64-b floating point multiplier with enhanced CG operation. - Hiroshi Makino; Hiroaki Suzuki; Hiroyuki Morinaka; Yasunobu Nakase; Koichiro Mashiko; Tadashi Sumi (IEEE J. Solid State Circuits, 1996)

A 1.9-GHz single chip IF transceiver for digital cordless phones. - Hisayasu Sato; Kenichi Kashiwagi; Kazuhito Niwano; Tetsuya Iga; Tatsuhiko Ikeda; Koichiro Mashiko; Tadashi Sumi; Koji Tsuchihashi (IEEE J. Solid State Circuits, 1996)

Leading-zero anticipatory logic for high-speed floating point addition. - Hiroaki Suzuki; Hiroyuki Morinaka; Hiroshi Makino; Yasunobu Nakase; Koichiro Mashiko; Tadashi Sumi (IEEE J. Solid State Circuits, 1996)

A 622-Mb/s bit/frame synchronizer for high-speed backplane data communication. - Tsutomu Yoshimura; Harufusa Kondoh; Yoshio Matsuda; Tadashi Sumi (IEEE J. Solid State Circuits, 1996)

Comments on "Leading-zero anticipatory logic for high-speed floating point addition" [with reply]. - Vojin G. Oklobdzija; Hiroaki Suzuki; Hiroyuki Morinaka; Hiroshi Makino; Yasunobu Nakase; Koichiro Mashiko; Tadashi Sumi (IEEE J. Solid State Circuits, 1997)

A multilevel QAM demodulator VLSI with wideband carrier recovery and dual equalizing mode. - Kazuya Yamanaka; Sumitaka Takeuchi; Shuji Murakami; Masayuki Koyama; Jun Ido; Takashi Fujiwara; Susumu Hirano; Keisuke Okada; Tadashi Sumi (IEEE J. Solid State Circuits, 1997)