Effect of resistance of TSV's on performance of boost converter for low power 3D SSD with NAND flash memories. - Tadashi Yasufuku; Koichi Ishida; Shinji Miyamoto; Hiroto Nakai; Makoto Takamiya; Takayasu Sakurai; Ken Takeuchi (3DIC, 2009)

Inductor design of 20-V boost converter for low power 3D solid state drive with NAND flash memories. - Tadashi Yasufuku; Koichi Ishida; Shinji Miyamoto; Hiroto Nakai; Makoto Takamiya; Takayasu Sakurai; Ken Takeuchi (ISLPED, 2009)

A stretchable EMI measurement sheet with 8×8 coil array, 2V organic CMOS decoder, and -70dBm EMI detection circuits in 0.18¼m CMOS. - Koichi Ishida; Naoki Masunaga; Zhiwei Zhou; Tadashi Yasufuku; Tsuyoshi Sekitani; Ute Zschieschang; Hagen Klauk; Makoto Takamiya; Takao Someya; Takayasu Sakurai (ISSCC, 2009)

A 1.8V 30nJ adaptive program-voltage (20V) generator for 3D-integrated NAND flash SSD. - Koichi Ishida; Tadashi Yasufuku; Shinji Miyamoto; Hiroto Nakai; Makoto Takamiya; Takayasu Sakurai; Ken Takeuchi (ISSCC, 2009)

Inductor and TSV Design of 20-V Boost Converter for Low Power 3D Solid State Drive with NAND Flash Memories. - Tadashi Yasufuku; Koichi Ishida; Shinji Miyamoto; Hiroto Nakai; Makoto Takamiya; Takayasu Sakurai; Ken Takeuchi (IEICE Trans. Electron., 2010)

Difficulty of Power Supply Voltage Scaling in Large Scale Subthreshold Logic Circuits. - Tadashi Yasufuku; Taro Niiyama; Piao Zhe; Koichi Ishida; Masami Murakata; Makoto Takamiya; Takayasu Sakurai (IEICE Trans. Electron., 2010)

Stretchable EMI Measurement Sheet With 8 ˟ 8 Coil Array, 2 V Organic CMOS Decoder, and 0.18 μ m Silicon CMOS LSIs for Electric and Magnetic Field Detection. - Koichi Ishida; Naoki Masunaga; Zhiwei Zhou; Tadashi Yasufuku; Tsuyoshi Sekitani; Ute Zschieschang; Hagen Klauk; Makoto Takamiya; Takao Someya; Takayasu Sakurai (IEEE J. Solid State Circuits, 2010)

A closed-form expression for estimating minimum operating voltage (VDDmin) of CMOS logic gates. - Hiroshi Fuketa; Satoshi Iida; Tadashi Yasufuku; Makoto Takamiya; Masahiro Nomura; Hirofumi Shinohara; Takayasu Sakurai (DAC, 2011)

12% Power reduction by within-functional-block fine-grained adaptive dual supply voltage control in logic circuits with 42 voltage domains. - Atsushi Muramatsu; Tadashi Yasufuku; Masahiro Nomura; Makoto Takamiya; Hirofumi Shinohara; Takayasu Sakurai (ESSCIRC, 2011)

12.7-times energy efficiency increase of 16-bit integer unit by power supply voltage (VDD) scaling from 1.2v to 310mv enabled by contention-less flip-flops (CLFF) and separated VDD between flip-flops and combinational logics. - Hiroshi Fuketa; Koji Hirairi; Tadashi Yasufuku; Makoto Takamiya; Masahiro Nomura; Hirofumi Shinohara; Takayasu Sakurai (ISLPED, 2011)

Investigation of determinant factors of minimum operating voltage of logic gates in 65-nm CMOS. - Tadashi Yasufuku; Satoshi Iida; Hiroshi Fuketa; Koji Hirairi; Masahiro Nomura; Makoto Takamiya; Takayasu Sakurai (ISLPED, 2011)

Power Supply Voltage Dependence of Within-Die Delay Variation of Regular Manual Layout and Irregular Place-and-Route Layout. - Tadashi Yasufuku; Yasumi Nakamura; Piao Zhe; Makoto Takamiya; Takayasu Sakurai (IEICE Trans. Electron., 2011)

1.8 V Low-Transient-Energy Adaptive Program-Voltage Generator Based on Boost Converter for 3D-Integrated NAND Flash SSD. - Koichi Ishida; Tadashi Yasufuku; Shinji Miyamoto; Hiroto Nakai; Makoto Takamiya; Takayasu Sakurai; Ken Takeuchi (IEEE J. Solid State Circuits, 2011)

24% Power reduction by post-fabrication dual supply voltage control of 64 voltage domains in VDDmin limited ultra low voltage logic circuits. - Tadashi Yasufuku; Koji Hirairi; Yu Pu; Yun Fei Zheng; Ryo Takahashi; Masato Sasaki; Hiroshi Fuketa; Atsushi Muramatsu; Masahiro Nomura; Hirofumi Shinohara; Makoto Takamiya; Takayasu Sakurai (ISQED, 2012)

13% Power reduction in 16b integer unit in 40nm CMOS by adaptive power supply voltage control with parity-based error prediction and detection (PEPD) and fully integrated digital LDO. - Koji Hirairi; Yasuyuki Okuma; Hiroshi Fuketa; Tadashi Yasufuku; Makoto Takamiya; Masahiro Nomura; Hirofumi Shinohara; Takayasu Sakurai (ISSCC, 2012)

Large Within-Die Gate Delay Variations in Sub-Threshold Logic Circuits at Low Temperature. - Ryo Takahashi; Hidehiro Takata; Tadashi Yasufuku; Hiroshi Fuketa; Makoto Takamiya; Masahiro Nomura; Hirofumi Shinohara; Takayasu Sakurai (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

Minimizing Energy of Integer Unit by Higher Voltage Flip-Flop: VDDmin-Aware Dual Supply Voltage Technique. - Hiroshi Fuketa; Koji Hirairi; Tadashi Yasufuku; Makoto Takamiya; Masahiro Nomura; Hirofumi Shinohara; Takayasu Sakurai (IEEE Trans. Very Large Scale Integr. Syst., 2013)

A 512Gb 3b/Cell 3D flash memory on a 96-word-line-layer technology. - Hiroshi Maejima; Kazushige Kanda; Susumu Fujimura; Teruo Takagiwa; Susumu Ozawa; Jumpei Sato; Yoshihiko Shindo; Manabu Sato; Naoaki Kanagawa; Junji Musha; Satoshi Inoue; Katsuaki Sakurai; et al. (ISSCC, 2018)