Matrix Order Reduction by Nodal Analysis Formulation and Relaxation-Based Fast Simulation for Power/Ground Plane. - Tadatoshi Sekine; Yuichi Tanji; Hideki Asai (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

CMOS Circuit Simulation Using Latency Insertion Method. - Tadatoshi Sekine; Hideki Asai (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

Predictor-corrector latency insertion method for fast transient analysis of ill-constructed circuits. - Hiroki Kurobe; Tadatoshi Sekine; Hideki Asai (ASP-DAC, 2012)

Unconditionally stable explicit method for the fast 3-D simulation of on-chip power distribution network with through silicon via. - Tadatoshi Sekine; Hideki Asai (ASP-DAC, 2013)

HIE-block latency insertion method for fast transient simulation of nonuniform multiconductor transmission lines. - Takahiro Takasaki; Tadatoshi Sekine; Hideki Asai (ASP-DAC, 2014)

ε κ-Curves: controlled local curvature extrema. - Kenjiro T. Miura 001; Rudrusamy U. Gobithaasan; Péter Salvi; Dan Wang; Tadatoshi Sekine; Shin Usuki; Jun-Ichi Inoguchi; Kenji Kajiwara (Vis. Comput., 2022)