Single-Chip Adaptive Transversal Filter IC Employing Switched Capacitor Technology. - Masa-Aki Yasumoto; Tadayoshi Enomoto; Kohjiro Watanabe; Tsutomu Ishihara (IEEE J. Sel. Areas Commun., 1984)

Video signal processor configuration by multiprocessor approach. - Takao Nishitani; Ichiro Tamitani; Hidenobu Harasaki; Masakatsu Yamashina; Tadayoshi Enomoto (ICASSP, 1986)

Realtime video signal processor module. - Hidenobu Harasaki; Ichiro Tamitani; Yukio Endo; Takao Nishitani; Masakatsu Yamashina; Tadayoshi Enomoto; Norio Suzuki (ICASSP, 1987)

A single-board video signal processor module employing newly developed LSI devices. - Hidenobu Harasaki; Ichiro Tamitani; Yukio Endo; Takao Nishitani; Masakatsu Yamashina; Tadayoshi Enomoto; Norio Suzuki (IEEE J. Sel. Areas Commun., 1988)

A microprogrammable real-time video signal processor (VSP) for motion compensation. - Masakazu Yamashina; Tadayoshi Enomoto; Takemitsu Kunio; Ichiro Tamitani; Hidenobu Harasaki; Yukio Endo; Takao Nishitani; Masao Satoh; Koichi Kikuchi (IEEE J. Solid State Circuits, 1988)

A 200-MHz 16-bit super high-speed signal processor (SSSP) LSI. - Masakazu Yamashina; Junichi Goto; Fuyuki Okamoto; Koichi Ando; Hachiro Yamada; Tadahiko Horiuchi; Kimiko Nakamura; Tadayoshi Enomoto (IEEE J. Solid State Circuits, 1989)

A 1.2-million transistor, 33-MHz, 20-b dictionary search processor (DISP) ULSI with a 160-kb CAM. - Masato Motomura; Jun Toyoura; Kazumi Hirata; Hideyuki Ooka; Hachiro Yamada; Tadayoshi Enomoto (IEEE J. Solid State Circuits, 1990)

250-MHz BiCMOS super-high-speed video signal processor (S-VSP) ULSI. - Junichi Goto; Koichi Ando; Toshiaki Inoue; Masakazu Yamashina; Hachiro Yamada; Tadayoshi Enomoto (IEEE J. Solid State Circuits, 1991)

A 200-MFLOPS 100-MHz 64-b BiCMOS vector-pipelined processor (VPP) ULSI. - Fuyuki Okamoto; Yasuhiko Hagihara; Chie Ohkubo; Naoki Nishi; Hachiro Yamada; Tadayoshi Enomoto (IEEE J. Solid State Circuits, 1991)

A 2 K-word dictionary search processor (DISP) LSI with an approximate word search capability. - Masato Motomura; Hachiro Yamada; Tadayoshi Enomoto (IEEE J. Solid State Circuits, 1992)

A 300-MHz 16-b BiCMOS video signal processor. - Toshiaki Inoue; Junichi Goto; Masakazu Yamashina; Kazumasa Suzuki; Masahiro Nomura; Youichi Koseki; Tohru Kimura; Takao Atsumo; Masato Motomura; Benjamin S. Shih; Tadahiko Horiuchi; Nobuhisa Hamatake; et al. (IEEE J. Solid State Circuits, 1993)

A 300-MHz 16-b 0.5-μm BiCMOS digital signal processor core LSI. - Masahiro Nomura; Masakazu Yamashina; Junichi Goto; Toshiaki Inoue; Kazumasa Suzuki; Masato Motomura; Youichi Koseki; Benjamin S. Shih; Tadahiko Horiuchi; Nobuhisa Hamatake; Kouichi Kumagai; Tadayoshi Enomoto; et al. (IEEE J. Solid State Circuits, 1994)

Fast motion estimation algorithm and low-power CMOS motion estimation array LSI for MPEG-2 encoding. - Tadayoshi Enomoto; Yasumasa Sasajima; Atsunori Hirobe; Tetsuya Ohsawa (ISCAS (4), 1999)

A fast motion estimation algorithm and low-power 0.13-um CMOS motion estimation circuits. - Tadayoshi Enomoto; Akira Kotabe (ISCAS (2), 2001)

A self-controllable voltage level (SVL) circuit and its low-power high-speed CMOS circuit applications. - Tadayoshi Enomoto; Yoshinori Oka; Hiroaki Shikano (IEEE J. Solid State Circuits, 2003)

A low dynamic power and low leakage power CMOS square-root circuit. - Tadayoshi Enomoto; Nobuaki Kobayashi (ISCAS (2), 2005)

A low dynamic power and low leakage power 90-nm CMOS square-root circuit. - Tadayoshi Enomoto; Nobuaki Kobayashi (ASP-DAC, 2006)

Low Dynamic Power and Low Leakage Power Techniques for CMOS Motion Estimation Circuits. - Nobuaki Kobayashi; Tomomi Ei; Tadayoshi Enomoto (IEICE Trans. Electron., 2006)

Low-Power High-Speed 180-nm CMOS Clock Drivers. - Tadayoshi Enomoto; Suguru Nagayama; Nobuaki Kobayashi (ASP-DAC, 2007)

A Multiple Block-matching Step (MBS) Algorithm for H.26x/MPEG4 Motion Estimation and a Low-Power CMOS Absolute Differential Accumulator Circuit. - Tadayoshi Enomoto; Nobuaki Kobayashi; Tomomi Ei (IEICE Trans. Electron., 2007)

A low-leakage current power 180-nm CMOS SRAM. - Tadayoshi Enomoto; Yuki Higuchi (ASP-DAC, 2008)

A low power 90-nm CMOS motion estimation processor implementing dynamic voltage and frequency scaling (DVFS) and fast motion estimation algorithm. - Nobuaki Kobayashi; Tadayoshi Enomoto (ISCAS, 2008)

Clock Driver Design for Low-Power High-Speed 90-nm CMOS Register Array. - Tadayoshi Enomoto; Suguru Nagayama; Hiroaki Shikano; Yousuke Hagiwara (IEICE Trans. Electron., 2008)

Fast Sub-sampling Block Matching Algorithm Employing Adaptively Assigned Sizes and Locations of Search Windows. - Tadayoshi Enomoto; Nobuaki Kobayashi; Shimon Isaka (ISCAS, 2009)

Foreword. - Tadayoshi Enomoto (IEICE Trans. Electron., 2009)

Low-Dynamic-Power and Low-Leakage-Power Techniques for CMOS Square-Root Circuit. - Tadayoshi Enomoto; Nobuaki Kobayashi (IEICE Trans. Electron., 2009)

A Large "Read" and "Write" Margins, Low Leakage Power, Six-Transistor 90-nm CMOS SRAM. - Tadayoshi Enomoto; Nobuaki Kobayashi (IEICE Trans. Electron., 2011)

A low power multimedia processor implementing dynamic voltage and frequency scaling technique. - Tadayoshi Enomoto; Nobuaki Kobayashi (ASP-DAC, 2013)

A Low Power Multimedia Processor Implementing Dynamic Voltage and Frequency Scaling Technique and Fast Motion Estimation Algorithm Called "Adaptively Assigned Breaking-Off Condition (A2BC)". - Tadayoshi Enomoto; Nobuaki Kobayashi (IEICE Trans. Electron., 2013)

A high stability, low supply voltage and low standby power six-transistor CMOS SRAM. - Nobuaki Kobayashi; Ryusuke Ito; Tadayoshi Enomoto (ASP-DAC, 2015)

Quantized Decoder Adaptively Predicting both Optimum Clock Frequency and Optimum Supply Voltage for a Dynamic Voltage and Frequency Scaling Controlled Multimedia Processor. - Nobuaki Kobayashi; Tadayoshi Enomoto (IEICE Trans. Electron., 2018)

Development of a Low Standby Power Six-Transistor CMOS SRAM Employing a Single Power Supply. - Nobuaki Kobayashi; Tadayoshi Enomoto (IEICE Trans. Electron., 2018)

Development of a high stability, low standby power six-transistor CMOS SRAM employing a single power supply. - Nobuaki Kobayashi; Tadayoshi Enomoto (ASP-DAC, 2019)

Low standby power CMOS delay flip-flop with data retention capability. - Nobuaki Kobayashi; Tadayoshi Enomoto (ASP-DAC, 2019)

Single-Power-Supply Six-Transistor CMOS SRAM Enabling Low-Voltage Writing, Low-Voltage Reading, and Low Standby Power Consumption. - Tadayoshi Enomoto; Nobuaki Kobayashi (IEICE Trans. Electron., 2023)