Reconfigurable architectures for mesh-arrays with PE and link faults. - Itsuo Takanami; Tadayoshi Horita (DFT, 1995)

Reconfiguration of 1 1/2 track-switch mesh-arrays with PE and bus faults. - Tadayoshi Horita; Itsuo Takanami (DFT, 1996)

Self-reconstruction of mesh-arrays with 1 1/2 -track switches by digital neural circuits. - Itsuo Takanami; Tadayoshi Horita (DFT, 1997)

A Polynomial Time Algorithm for Reconfiguring the 1 1/2 Track-Switch Model with PE and Bus faults. - Tadayoshi Horita; Itsuo Takanami (ISPAN, 1997)

A built-in self-reconfigurable scheme for 3D mesh arrays. - Itsuo Takanami; Tadayoshi Horita (ISPAN, 1997)

Fault Tolerant Processor Arrays Based on 1 1/2-Track Switch with Generalized Spare Distributions. - Tadayoshi Horita; Itsuo Takanami (ISPAN, 1999)

A System for Efficiently Self-Reconstructing E-1½-Track Switch Torus Arrays. - Tadayoshi Horita; Itsuo Takanami (ISPAN, 2000)

A System for Efficiently Self-Reconstructing 1½-Track Switch Torus Arrays. - Tadayoshi Horita; Itsuo Takanami (PDPTA, 2000)

Fault-Tolerant Processor Arrays Based on the 1½-Track Switches with Flexible Spare Distributions. - Tadayoshi Horita; Itsuo Takanami (IEEE Trans. Computers, 2000)

Analytical Results for Reconfiguration of E-11/2- Track Switch Torus Arrays with Multiple Fault Types. - Tadayoshi Horita; Itsuo Takanami (PRDC, 2001)

A Multiple-Weight-and-Neuron-Fault Tolerant Digital Multilayer Neural Network. - Tadayoshi Horita; Takurou Murata; Itsuo Takanami (DFT, 2006)

An Analysis for Fault-Tolerant 3D Processor Arrays Using 1.5-Track Switches. - Tadayoshi Horita; Yuuji Katou; Itsuo Takanami (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

Learning Algorithms Which Make Multilayer Neural Networks Multiple-Weight-and-Neuron-Fault Tolerant. - Tadayoshi Horita; Itsuo Takanami; Masatoshi Mori (IEICE Trans. Inf. Syst., 2008)

A Computer Cluster for Tests of Parallel Programming Environments Including Operating Systems. - Tadayoshi Horita; Koichi Kitano; Koji Teramoto (PDPTA, 2009)

An Implementation of a Fault-Tolerant 2D Systolic Array on FPGAs and Its Evaluation. - Tadayoshi Horita; Itsuo Takanami (PDPTA, 2009)

Novel Value Injection Learning Methods Which Make Multilayer Neural Networks Multiple-Weight-and-Neuron-Fault Tolerant. - Kazuhiro Nishimura; Tadayoshi Horita; Masato Otsu; Itsuo Takanami (PDPTA, 2009)

An FPGA-based fast classifier with high generalization property. - Tadayoshi Horita; Itsuo Takanami (SIGARCH Comput. Archit. News, 2010)

An FPGA-Based Fault-Tolerant 2D Systolic Array for Matrix Multiplications. - Tadayoshi Horita; Itsuo Takanami (Trans. Comput. Sci., 2011)

A Built-in Circuit for Self-Repairing Mesh-Connected Processor Arrays by Direct Spare Replacement. - Itsuo Takanami; Tadayoshi Horita (PRDC, 2012)

An FPGA-based multiple-weight-and-neuron-fault tolerant digital multilayer perceptron. - Tadayoshi Horita; Itsuo Takanami (Neurocomputing, 2013)

A GPGPU-Based Acceleration of Fault-Tolerant MLP Learnings. - Tadayoshi Horita; Itsuo Takanami; Masakazu Akiba; Mina Terauchi; Tsuneo Kanno (MCSoC, 2014)

Multilayer Perceptrons Which Are Tolerant to Multiple Faults and Learnings to Realize Them. - Tadayoshi Horita; Itsuo Takanami; Kazuhiro Nishimura (Trans. Comput. Sci., 2014)

An FPGA-Based Multiple-Weight-and-Neuron-Fault Tolerant Digital Multilayer Perceptron (Full Version). - Tadayoshi Horita; Itsuo Takanami; Masakazu Akiba; Mina Terauchi; Tsuneo Kanno (Trans. Comput. Sci., 2015)

A Built-in Self-repair Circuit for Restructuring Mesh-Connected Processor Arrays by Direct Spare Replacement. - Itsuo Takanami; Tadayoshi Horita; Masakazu Akiba; Mina Terauchi; Tsuneo Kanno (Trans. Comput. Sci., 2016)