A channel-erasing 1.8-V-only 32-Mb NOR flash EEPROM with a bitline direct sensing scheme. - Shigeru Atsumi; Akira Umezawa; Toru Tanzawa; Tadayuki Taura; Hitoshi Shiga; Yoshinori Takano; Takeshi Miyaba; Michiharu Matsui; Hiroshi Watanabe; Kazuaki Isobe; Shota Kitamura; Seiji Yamada; et al. (IEEE J. Solid State Circuits, 2000)

Design of a sense circuit for low-voltage flash memories. - Toru Tanzawa; Yoshinori Takano; Tadayuki Taura; Shigeru Atsumi (IEEE J. Solid State Circuits, 2000)

Wordline voltage generating system for low-power low-voltage flash memories. - Toru Tanzawa; Akira Umezawa; Masao Kuriyama; Tadayuki Taura; Hironori Banba; Takeshi Miyaba; Hitoshi Shiga; Yoshinori Takano; Shigeru Atsumi (IEEE J. Solid State Circuits, 2001)

A 44-mm2 four-bank eight-word page-read 64-Mb flash memory with flexible block redundancy and fast accurate word-line voltage controller. - Toru Tanzawa; Akira Umezawa; Tadayuki Taura; Hitoshi Shiga; Tokumasa Hara; Yoshinori Takano; Takeshi Miyaba; Naoya Tokiwa; Kentaro Watanabe; Hiroshi Watanabe; Kazunori Masuda; Kiyomi Naruke; et al. (IEEE J. Solid State Circuits, 2002)

High-Speed Digital Double Sampling with Analog CDS on Column Parallel ADC Architecture for Low-Noise Active Pixel Sensor. - Yoshikazu Nitta; Yoshinori Muramatsu; Kiyotaka Amano; Takayuki Toyama; Jun Yamamoto; Koji Mishina; Atsushi Suzuki; Tadayuki Taura; Akihiko Kato; Masaru Kikuchi; Yukihiro Yasui; Hideo Nomura; et al. (ISSCC, 2006)

An 83dB-dynamic-range single-exposure global-shutter CMOS image sensor with in-pixel dual storage. - Masaki Sakakibara; Yusuke Oike; Takafumi Takatsuka; Akihiko Kato; Katsumi Honda; Tadayuki Taura; Takashi Machida; Jun Okuno; Atsuhiro Ando; Taketo Fukuro; Tomohiko Asatsuma; Suzunori Endo; et al. (ISSCC, 2012)

A back-illuminated global-shutter CMOS image sensor with pixel-parallel 14b subthreshold ADC. - Masaki Sakakibara; Koji Ogawa; Shin Sakai; Yasuhisa Tochigi; Katsumi Honda; Hidekazu Kikuchi; Takuya Wada; Yasunobu Kamikubo; Tsukasa Miura; Masahiko Nakamizo; Naoki Jyo; Ryo Hayashibara; et al. (ISSCC, 2018)

A 6.9-µm Pixel-Pitch Back-Illuminated Global Shutter CMOS Image Sensor With Pixel-Parallel 14-Bit Subthreshold ADC. - Masaki Sakakibara; Koji Ogawa; Shin Sakai; Yasuhisa Tochigi; Katsumi Honda; Hidekazu Kikuchi; Takuya Wada; Yasunobu Kamikubo; Tsukasa Miura; Masahiko Nakamizo; Naoki Jyo; Ryo Hayashibara; et al. (IEEE J. Solid State Circuits, 2018)

A 6.9 μm Pixel-Pitch 3D Stacked Global Shutter CMOS Image Sensor with 3M Cu-Cu connections. - Tsukasa Miura; Masaki Sakakibara; Hirotsugu Takahashi; Tadayuki Taura; Keiji Tatani; Yusuke Oike; Takayuki Ezaki (3DIC, 2019)

High-Density and Large-Scale MEA System Featuring 236, 880 Electrodes at 11.72μm Pitch for Neuronal Network Analysis. - Yuri Kato; Yoshihisa Matoba; Katsumi Honda; Koji Ogawa; Kan Shimizu; Masataka Maehara; Atsushi Fujiwara; Aoi Odawara; Chigusa Yamane; Naohiko Kimizuka; Jun Ogi; Tadayuki Taura; et al. (VLSI Circuits, 2020)