A 3.2 GHz 178fsrms Jitter Injection Locked Clock Multiplier Using Sub-Sampling FTL and DLL for In-Band Noise Improvement. - Dong-Hyun Yoon; Dong-Kyu Jung; Kiho Seong; Tae-Hyeok Eom; Jae-Soub Han; Ju Eon Kim; Tony Tae-Hyoung Kim; Kwang-Hyun Baek (A-SSCC, 2021)

A Reference-Sampling Based Calibration-Free Fractional-N PLL with a PI-Linked Sampling Clock Generator. - Jae-Soub Han; Tae-Hyeok Eom; Seong-Wook Choi; Kiho Seong; Dong-Hyun Yoon; Tony Tae-Hyoung Kim; Kwang-Hyun Baek; Yong Shim (Sensors, 2021)