A Digital PLL with 5-Phase Digital PFD for Low Long-term Jitter Clock Recovery. - Tae-Young Oh; Seung-Hyun Yi; Sung-Hyun Yang; Byong-Chan Lim; Kuk-Tae Hong (CICC, 2006)

A 7Gb/s/pin GDDR5 SDRAM with 2.5ns bank-to-bank active time and no bank-group restriction. - Tae-Young Oh; Young-Soo Sohn; Seung-Jun Bae; Min-Sang Park; Ji-Hoon Lim; Yong-Ki Cho; Dae-Hyun Kim 003; Dong-Min Kim; Hye-Ran Kim; Hyun-Joong Kim; Jin-Hyun Kim; Jin-Kook Kim; et al. (ISSCC, 2010)

A 40nm 2Gb 7Gb/s/pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BW. - Seung-Jun Bae; Young-Soo Sohn; Tae-Young Oh; Si-Hong Kim; Yun-Seok Yang; Dae-Hyun Kim 003; Sang-Hyup Kwak; Ho-Seok Seol; Chang-Ho Shin; Min-Sang Park; Gong-Heom Han; Byeong-Cheol Kim; et al. (ISSCC, 2011)

A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction. - Tae-Young Oh; Young-Soo Sohn; Seung-Jun Bae; Min-Sang Park; Ji-Hoon Lim; Yong-Ki Cho; Dae-Hyun Kim 003; Dong-Min Kim; Hye-Ran Kim; Hyun-Joong Kim; Jin-Hyun Kim; Jin-Kook Kim; et al. (IEEE J. Solid State Circuits, 2011)

25.1 A 3.2Gb/s/pin 8Gb 1.0V LPDDR4 SDRAM with integrated ECC engine for sub-1V DRAM core operation. - Tae-Young Oh; Hoeju Chung; Young-Chul Cho; Jang-Woo Ryu; Kiwon Lee; Changyoung Lee; Jin-Il Lee; Hyoung-Joo Kim 002; Min-Soo Jang; Gong-Heum Han; Kihan Kim; Daesik Moon; et al. (ISSCC, 2014)

A PSRR Enhancing Method for GRO TDC Based Clock Generation Systems. - Yutao Liu; Yizhi Han; Woogeun Rhee; Tae-Young Oh; Zhihua Wang 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

A 3.2 Gbps/pin 8 Gbit 1.0 V LPDDR4 SDRAM With Integrated ECC Engine for Sub-1 V DRAM Core Operation. - Tae-Young Oh; Hoeju Chung; Jun-Young Park; Ki-Won Lee; Seung-Hoon Oh; Su-Yeon Doo; Hyoung-Joo Kim 002; ChangYong Lee; Hye-Ran Kim; Jong-Ho Lee; Jin-Il Lee; Kyung-Soo Ha; et al. (IEEE J. Solid State Circuits, 2015)

Dual-loop 2-step ZQ calibration for dedicated power supply voltage in LPDDR4 SDRAM. - Chang-Kyo Lee; Junha Lee; Kiho Kim; Jin-Seok Heo; Gil-Hoon Cha; Jin-Hyeok Baek; Daesik Moon; Yoon-Joo Eom; Tae-Sung Kim; Hyunyoon Cho; Young Hoon Son; Seonghwan Kim 002; et al. (A-SSCC, 2017)

23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme. - Chang-Kyo Lee; Yoon-Joo Eom; Jin-Hee Park; Junha Lee; Hye-Ran Kim; Kihan Kim; Young Choi; Ho-Jun Chang; Jonghyuk Kim; Jong-Min Bang; Seungjun Shin; Hanna Park; et al. (ISSCC, 2017)

A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power. - Kyung-Soo Ha; Chang-Kyo Lee; Dongkeon Lee; Daesik Moon; Jin-Hun Jang; Hyong-Ryol Hwang; Hyung-Joon Chi; Junghwan Park; Seungjun Shin; Dukha Park; Sang-Yun Kim 001; Sukhyun Lim; et al. (ISSCC, 2019)

A 7.5 Gb/s/pin 8-Gb LPDDR5 SDRAM With Various High-Speed and Low-Power Techniques. - Kyung-Soo Ha; Seungseob Lee; Youn-Sik Park; Hyuck-Joon Kwon; Tae-Young Oh; Young-Soo Sohn; Seung-Jun Bae; Kwang-Il Park; Jung-Bae Lee; Chang-Kyo Lee; Dongkeon Lee; Daesik Moon; et al. (IEEE J. Solid State Circuits, 2020)

Industry's First 7.2 Gbps 512GB DDR5 Module. - Sung Joo Park; Jonghoon J. Kim; Kun Joo; Young-Ho Lee; Kyoungsun Kim; Young-Tae Kim; Woo-Jin Na; IkJoon Choi; Hye-Seung Yu; Wonyoung Kim; Ju-Yeon Jung; Jaejun Lee; et al. (HCS, 2021)

A 16Gb 27Gb/s/pin T-coil based GDDR6 DRAM with Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus. - Daewoong Lee; Hye-Jung Kwon; Daehyun Kwon; Jaehyeok Baek; Chulhee Cho; Sanghoon Kim; Donggun An; Chulsoon Chang; Unhak Lim; Jiyeon Im; Wonju Sung; Hye-Ran Kim; et al. (ISSCC, 2022)

A 1.01V 8.5Gb/s/pin 16Gb LPDDR5x SDRAM with Self-Pre-Emphasized Stacked-Tx, Supply Voltage Insensitive Rx, and Optimized Clock Using 4th-Generation 10nm DRAM Process for High-Speed and Low-Power Applications. - Hyun-A. Ahn; Yoo-Chang Sung; Yong-Hun Kim; Janghoo Kim; Kihan Kim; Donghun Lee; Young-Gil Go; Jae-Woo Lee; Jae-Woo Jung; Yong-Hyun Kim; Garam Choi; Jun-Seo Park; et al. (A-SSCC, 2023)

A 16-Gb T-Coil-Based GDDR6 DRAM With Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus Achieving 27-Gb/s/Pin in NRZ. - Daewoong Lee; Jaehyeok Baek; Hye-Jung Kwon; Daehyun Kwon; Chulhee Cho; Sang-Hoon Kim; Donggun An; Chulsoon Chang; Unhak Lim; Jiyeon Im; Wonju Sung; Hye-Ran Kim; et al. (IEEE J. Solid State Circuits, 2023)

A 1.06V 5Gb/s/pin 16Gb LPDDR4x DRAM Adopting Sense Amplifier with AC-Coupled Equalizer, Stacked Output Driver, and Clock MUX with Inverter-Based Transmission Gate for Mobile and Automotive Application. - Young-Gil Go; Hyun-A. Ahn; Yoo-Chang Sung; Myung-Hun Jung; Ji-Geon Yeom; Hun-Dae Choi; Janghoo Kim; Hyunjin Ko; Miyoung Woo; Seong-O. Huh; Seung-Jun Bae; Tae-Young Oh (A-SSCC, 2024)

13.6 A 16Gb 37Gb/s GDDR7 DRAM with PAM3-Optimized TRX Equalization and ZQ Calibration. - Sung-Yong Cho; Moon-Chul Choi; Jaehyeok Baek; Donggun An; Sanghoon Kim; Daewoong Lee; Seongyeal Yang; Gil-Young Kang; Juseop Park; Kyungho Lee; Hwan-Chul Jung; Gun-hee Cho; et al. (ISSCC, 2024)

13.2 A 32Gb 8.0Gb/s/pin DDR5 SDRAM with a Symmetric-Mosaic Architecture in a 5th-Generation 10nm DRAM Process. - IkJoon Choi; Seunghwan Hong; Kihyun Kim; Jeongsik Hwang; Seunghan Woo; Young-Sang Kim; Cheongryong Cho; Eun-Young Lee; Hun-Jae Lee; Min-Su Jung; Hee-Yun Jung; Ju-Seong Hwang; et al. (ISSCC, 2024)

A 1.01-V 8.5-Gb/s/pin 16-Gb LPDDR5x SDRAM With Advanced I/O Circuitry for High-Speed and Low-Power Applications. - Hyun-A. Ahn; Yoo-Chang Sung; Yong-Hun Kim; Janghoo Kim; Kihan Kim; Dong-Hun Lee; Young-Gil Go; Jae-Woo Lee; Jae-Woo Jung; Yong-Hyun Kim; Garam Choi; Jun-Seo Park; et al. (IEEE J. Solid State Circuits, 2024)

A PAM-4 Crosstalk Compensation Receiver Using an RC Circuit per Pin for 4×24 Gb/s/Pin Single-Ended DRAM Interface. - Ho-Jun Kim; Sung-Yong Cho; Tae-Young Oh; Hong-June Park (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

A 16Gb 12.7Gb/s/pin LPDDR5-Ultra-Pro DRAM with 4-Phase Self-Calibration and AC-Coupled Transceiver Equalization in a 5th-Generation 10nm DRAM Process. - Jin-Hyeok Baek; Jang-Hoo Kim; Yoo-Chang Sung; Jae-Woo Jeong; Jin-Kwan Park; Hyun-Kyu Oh; Bo-Hyeon Lee; Dong-Wan Ko; Tae-Seob Oh; Seung-Gi Hong; Chang-Ki Kwon; Daihyun Lim; et al. (ISSCC, 2025)

30.3 A 24Gb 42.5Gb/s GDDR7 DRAM with Low-Power WCK Distribution, an RC-Optimized Dual-Emphasis TX, and Voltage/Time-Margin-Enhanced Power Reduction. - Sang-Hoon Kim; Jaehyeok Baek; Moon-Chul Choi; Daewoong Lee; Donggun An; Se-Mi Kim; Yeonggeun Song; Minkyo Shim; Sung-Yong Cho; Dongha Lee; Gun-hee Cho; Inwoo Jun; et al. (ISSCC, 2025)

A 16-Gb 37-Gb/s GDDR7 DRAM With PAM3-Optimized TRX Equalization and ZQ Calibration. - Sung-Yong Cho; Moon-Chul Choi; Jaehyeok Baek; Donggun An; Sang-Hoon Kim; Daewoong Lee; Seongyeal Yang; Se-Mi Kim; Gil-Young Kang; Juseop Park; Kyung-Ho Lee; Hwan-Chul Jung; et al. (IEEE J. Solid State Circuits, 2025)