An Analytical Model to Study Optimal Area Breakdown between Cores and Caches in a Chip Multiprocessor. - Taecheol Oh; Hyunjin Lee; Kiyeon Lee; Sangyeun Cho (ISVLSI, 2009)

An Analytical Performance Model for Co-management of Last-Level Cache and Bandwidth Sharing. - Taecheol Oh; Kiyeon Lee; Sangyeun Cho (MASCOTS, 2011)