Multi-bit flip-flop generation considering multi-corner multi-mode timing constraint. - Taehee Lee 003; JongWon Yi; Joon-Sung Yang (ISCAS, 2016)

Temperature and voltage droop-aware test scheduling during scan shift operation. - Taehee Lee 003; YongJoon Kim; Joon-Sung Yang (IEICE Electron. Express, 2016)

Physical-aware gating element insertion for thermal-safe scan shift operation. - Taehee Lee 003; Joon-Sung Yang (IEICE Electron. Express, 2017)

Enhancing Test Compression With Dependency Analysis for Multiple Expansion Ratios. - Taehee Lee 003; Nur A. Touba; Joon-Sung Yang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Clock Network Optimization With Multibit Flip-Flop Generation Considering Multicorner Multimode Timing Constraint. - Taehee Lee 003; David Z. Pan; Joon-Sung Yang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)