An injection locked PLL for power supply variation robustness using negative phase shift phenomenon of injection locked frequency divider. - Dongil Lee; Taeho Lee 001; Yong-Hun Kim; Young-Ju Kim 001; Lee-Sup Kim (CICC, 2015)

An integrated time register and arithmetic circuit with combined operation for time-domain signal processing. - Daewoong Lee; Dongil Lee; Taeho Lee 001; Yong-Hun Kim; Lee-Sup Kim (ISCAS, 2015)

An 11.5 Gb/s 1/4th Baud-Rate CTLE and Two-Tap DFE With Boosted High Frequency Gain in 110-nm CMOS. - Yong-Hun Kim; Young-Ju Kim 001; Tae-Ho Lee 001; Lee-Sup Kim (IEEE Trans. Very Large Scale Integr. Syst., 2015)

A 21%-Jitter-Improved Self-Aligned Dividerless Injection-Locked PLL With a VCO Control Voltage Ripple-Compensated Phase Detector. - Dongil Lee; Taeho Lee 001; Young-Ju Kim 001; Lee-Sup Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

A 21-Gbit/s 1.63-pJ/bit Adaptive CTLE and One-Tap DFE With Single Loop Spectrum Balancing Method. - Yong-Hun Kim; Young-Ju Kim 001; Taeho Lee 001; Lee-Sup Kim (IEEE Trans. Very Large Scale Integr. Syst., 2016)

A 5-Gb/s 2.67-mW/Gb/s Digital Clock and Data Recovery With Hybrid Dithering Using a Time-Dithered Delta-Sigma Modulator. - Taeho Lee 001; Yong-Hun Kim; Jaehyeong Sim; Jun-Seok Park; Lee-Sup Kim (IEEE Trans. Very Large Scale Integr. Syst., 2016)

An Input Data and Power Noise Inducing Clock Jitter Tolerant Reference-Less Digital CDR for LCD Intra-Panel Interface. - Yong-Hun Kim; Taeho Lee 001; Hyun-Kyu Jeon; Dongil Lee; Lee-Sup Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

A 5-Gb/s Digital Clock and Data Recovery Circuit With Reduced DCO Supply Noise Sensitivity Utilizing Coupling Network. - Taeho Lee 001; Yong-Hun Kim; Lee-Sup Kim (IEEE Trans. Very Large Scale Integr. Syst., 2017)