Weighted Capacitor Digital-to-Analog Converter adopting extensive charge sharing scheme. - Taeho Lim; K. J. Kim; K. H. Ahn; Jin-Sup Kim (APCCAS, 2010)

An optimal gate design for the synthesis of ternary logic circuits. - Sunmean Kim; Taeho Lim; Seokhyeong Kang (ASP-DAC, 2018)

Analysis and Solution of CNN Accuracy Reduction over Channel Loop Tiling. - Yesung Kang; Yoonho Park; Sunghoon Kim; Eunji Kwon; Taeho Lim; Sangyun Oh; Mingyu Woo; Seokhyeong Kang (DATE, 2020)