A SCAN Chain Generator for Verification of Full-Custom Integrated Circuits. - Taeho Shin; Jaeduk Han (ISOCC, 2021)

A Custom IC Layout Generation Engine Based on Dynamic Templates and Grids. - Taeho Shin; Dongjun Lee; Dongwhee Kim; Gaeryun Sung; Wookjin Shin; Yunseong Jo; Hyungjoo Park; Jaeduk Han (CoRR, 2022)

A 100Gb/s 1.6Vppd PAM-8 Transmitter with High-Swing 3+1 Hybrid FFE Taps in 40nm. - Jeonghyu Yang; Eunji Song; Seungwook Hong; Dongjun Lee; Sangwan Lee; Hyunwoo Im; Taeho Shin; Jaeduk Han (ISSCC, 2023)

LAYGO2: A Custom Layout Generation Engine Based on Dynamic Templates and Grids for Advanced CMOS Technologies. - Taeho Shin; Dongjun Lee; Dongwhee Kim; Gaeryun Sung; Wookjin Shin; Yunseong Jo; Hyungjoo Park; Jaeduk Han (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

A 100-Gb/s PAM-8 Transmitter With 3-Tap FFE and High-Swing Hybrid Driver in 40-nm CMOS Technology. - Youngmin Oh; Hyunwoo Im; Jeonghyu Yang; Eunji Song; Dongjun Lee; Sangwan Lee; Taeho Shin; Jaeduk Han (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A 56-Gb/s 0.39-pJ/bit PAM-4 Transmitter Frontend with Shunt-Ffe Tail-Less Driver and External Bias-Tees. - Yooseong Jang; Seokmin Yun; Jeonghyu Yang; Taeho Shin; Eunji Song; Jaeduk Han (ISCAS, 2025)

Process-Portable Layout Generation of High-Speed Digital Circuit Using Standard Cells in FinFET. - Taeseung Kang; Taeho Shin; Heejun Kim; Jaeduk Han (SMACD, 2025)

100-112-Gb/s 1.6-Vppd PAM-8 Transmitters With High-Swing 3 + 1 Hybrid FFE Taps in 40-nm Technology. - Eunji Song; Jeonghyu Yang; Youngmin Oh; Seungwook Hong; Dongjun Lee; Sangwan Lee; Hyunwoo Im; Taeho Shin; Jaeduk Han (IEEE J. Solid State Circuits, 2025)