A 5Gb/s 2×2 MIMO crosstalk cancellation scheme for high-speed I/Os. - Taehyoun Oh; Ramesh Harjani (CICC, 2010)

A 6-Gb/s MIMO Crosstalk Cancellation Scheme for High-Speed I/Os. - Taehyoun Oh; Ramesh Harjani (IEEE J. Solid State Circuits, 2011)

4×12 Gb/s 0.96 pJ/b/lane analog-IIR crosstalk cancellation and signal reutilization receiver for single-ended I/Os in 65 nm CMOS. - Taehyoun Oh; Ramesh Harjani (VLSIC, 2012)

A 12-Gb/s Multichannel I/O Using MIMO Crosstalk Cancellation and Signal Reutilization in 65-nm CMOS. - Taehyoun Oh; Ramesh Harjani (IEEE J. Solid State Circuits, 2013)

A 4Gb/s, 370µA low-power Tx FIR driver for LPDDR4 applications. - Taehyoun Oh; Myung Chul Park; Yun Seong Eo (IEICE Electron. Express, 2014)

A 4.1mA adaptive duty-cycle corrector loop with background calibration in 45nm CMOS process. - Esther Kim; Deokgwan Jeong; Taehyoun Oh (ISOCC, 2016)

Pseudo-Reference Counter-Based FLL for 6 Gb/s Reference-Less CDR in 65-nm CMOS. - Sanggeun Lee; Ramesh Harjani; Taehyoun Oh (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

Linear Characteristic Analysis of High-Resolution Counter-Based Frequency Detector in Type-I Digital PLL. - Taehyoun Oh; Joonho Gil; Ramesh Harjani (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A Highly Integrated Radio Frequency Receiver RF CMOS Module for Core Body Temperature Thermometer. - Ikhwan Kim; Won Il Jang; Hyeon-Sik Hwang; Byeong-Jae Seo; Dong-Min Lee; Ji-Ho Han; Jaewoo Shin; Young-Ro Yoon; Taehyoun Oh; Hyung-Chul Park; Eun Seong Kim; Yun Seong Eo; et al. (IEEE Access, 2023)

A 3.5 to 4.7-GHz Fractional-N ADPLL With a Low-Power Time-Interleaved GRO-TDC of 6.2-ps Resolution in 65-nm CMOS Process. - Kyoung-Ub Cho; Joonho Gil; Chulhyun Park; Kyu-Jin Cho; Jaewoo Shin; Eun Seong Kim; Yun Seong Eo; Ramesh Harjani; Nam-Young Kim; Taehyoun Oh (IEEE Access, 2024)