Accurate compact model extraction for on-chip coplanar waveguides. - Taeik Kim; Xiaoyong Li 001; David J. Allstot (ISCAS (4), 2003)

On-chip inductor structures: a comparative study. - Srinivas Kodali; Taeik Kim; David J. Allstot (ISCAS (1), 2003)

A tunable transmission line phase shifter (TTPS). - Taeik Kim; David J. Allstot (ISCAS (1), 2004)

Compact model generation for on-chip transmission lines. - Taeik Kim; Xiaoyong Li 001; David J. Allstot (IEEE Trans. Circuits Syst. I Regul. Pap., 2004)

A 0.004mm2 250μW ΔΣ TDC with time-difference accumulator and a 0.012mm2 2.5mW bang-bang digital PLL using PRNG for low-power SoC applications. - Jong-Phil Hong; Sung-Jin Kim; Jenlung Liu; Nan Xing; Tae-Kwang Jang; Jaejin Park; Jihyun F. Kim; Taeik Kim; Hojin Park (ISSCC, 2012)

A 0.026mm2 5.3mW 32-to-2000MHz digital fractional-N phase locked-loop using a phase-interpolating phase-to-digital converter. - Tae-Kwang Jang; Nan Xing; Frank Liu 003; Jungeun Shin; Hyungreal Ryu; Jihyun F. Kim; Taeik Kim; Jaejin Park; Hojin Park (ISSCC, 2013)

A 0.032mm2 3.1mW synthesized pixel clock generator with 30psrms integrated jitter and 10-to-630MHz DCO tuning range. - Wooseok Kim; Jaejin Park; Jihyun F. Kim; Taeik Kim; Hojin Park; Deog-Kyoon Jeong (ISSCC, 2013)

A 0.010mm2 9.92psrms low tracking jitter pixel clock generator with a divider initializer and a nearest phase selector in 28nm CMOS technology. - Kangyeop Choo; Sung-Jin Kim; Wooseok Kim; Jihyun F. Kim; Taeik Kim; Hojin Park (CICC, 2014)

15.2 A 0.012mm2 3.1mW bang-bang digital fractional-N PLL with a power-supply-noise cancellation technique and a walking-one-phase-selection fractional frequency divider. - Jenlung Liu; Tae-Kwang Jang; Yonghee Lee; Jungeun Shin; Seunghoon Lee; Taeik Kim; Jaejin Park; Hojin Park (ISSCC, 2014)

A 0.63ps, 12b, synchronous cyclic TDC using a time adder for on-chip jitter measurement of a SoC in 28nm CMOS technology. - Sung-Jin Kim; Taeik Kim; Hojin Park (VLSIC, 2014)

A 72μW, 2.4GHz, 11.7% tuning range, 212dBc/Hz FoM LC-VCO in 65nm CMOS. - Joo-Myoung Kim; Jae-Seung Lee; Sun-a Kim; Taeik Kim; Hojin Park; Sang-Gug Lee 001 (CICC, 2015)

15.5 A 0.6V 1.17ps PVT-tolerant and synthesizable time-to-digital converter using stochastic phase interpolation with 16× spatial redundancy in 14nm FinFET technology. - Sung-Jin Kim; Wooseok Kim; Minyoung Song; Jihyun F. Kim; Taeik Kim; Hojin Park (ISSCC, 2015)

14.4 A 5GHz -95dBc-reference-Spur 9.5mW digital fractional-N PLL using reference-multiplied time-to-digital converter and reference-spur cancellation in 65nm CMOS. - Hyojun Kim; Jinwoo Sang; Hyunik Kim; Youngwoo Jo; Taeik Kim; Hojin Park; SeongHwan Cho (ISSCC, 2015)

14.8 A 0.009mm2 2.06mW 32-to-2000MHz 2nd-order ΔΣ analogous bang-bang digital PLL with feed-forward delay-locked and phase-locked operations in 14nm FinFET technology. - Minyoung Song; Taeik Kim; Jihyun F. Kim; Wooseok Kim; Sung-Jin Kim; Hojin Park (ISSCC, 2015)

A 0.35-0.5-V 18-152 MHz Digitally Controlled Relaxation Oscillator With Adaptive Threshold Calibration in 65-nm CMOS. - Yudong Zhang 006; Woogeun Rhee; Taeik Kim; Hojin Park; Zhihua Wang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

19.3 A 2.4GHz 1.5mW digital MDLL using pulse-width comparator and double injection technique in 28nm CMOS. - Hyunik Kim; Yongjo Kim; Taeik Kim; Hojin Park; SeongHwan Cho (ISSCC, 2016)

A 2.4-GHz 1.5-mW Digital Multiplying Delay-Locked Loop Using Pulsewidth Comparator and Double Injection Technique. - Hyunik Kim; Yongjo Kim; Taeik Kim; Hyung Jong Ko; SeongHwan Cho (IEEE J. Solid State Circuits, 2017)

A 0.015-mm2 Inductorless 32-GHz Clock Generator With Wide Frequency-Tuning Range in 28-nm CMOS Technology. - Gyu-Seob Jeong; Wooseok Kim; Jaejin Park; Taeik Kim; Hojin Park; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

A Crystal-Less Programmable Clock Generator with RC-LC Hybrid Oscillator for GHz Applications in 14 nm FinFET CMOS. - Jeongho Hwang; Gyu-Seob Jeong; Sang-Hyeok Chu; Wooseok Kim; Taeik Kim; Deog-Kyoon Jeong (BCICTS, 2018)

A 0.02mm2 fully synthesizable period-jitter sensor using stochastic TDC without reference clock and calibration in 10nm CMOS technology. - Kangyeop Choo; Hyunik Kim; Wooseok Kim; Jihyun F. Kim; Taeik Kim; Hyung Jong Ko (ISSCC, 2018)

Session 19 overview: Sensors and interfaces: Analog subcommittee. - Man-Kay Law; Taeik Kim; Kofi A. A. Makinwa (ISSCC, 2018)

A 5GHz 200kHz/5000ppm Spread-Spectrum Clock Generator with Calibration-Free Two-Point Modulation Using a Nested-Loop BBPLL. - Xiaohua Huang; Kunnong Zeng; Yuguang Liu; Woogeun Rhee; Taeik Kim; Zhihua Wang 001 (CICC, 2019)

A Programmable On-Chip Reference Oscillator With Slow-Wave Coplanar Waveguide in 14-nm FinFET CMOS. - Jeongho Hwang; Sang-Hyeok Chu; Gyu-Seob Jeong; Yeojoon Youn; Wooseok Kim; Taeik Kim; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

Session 5 Overview: Analog Interfaces Analog Subcommittee. - Jens Anders; Taeik Kim; David T. Blaauw (ISSCC, 2021)