Double-Gated Asymmetric Floating-Gate-Based Synaptic Device for Effective Performance Enhancement Through Online Learning. - Dong-Hyun Ryu; Tae-Hyung Kim; Taejin Jang; Junsu Yu; Jong-Ho Lee 002; Byung-Gook Park (IEEE Access, 2020)

A Single-Path Digital-IF Receiver Supporting Inter/Intra 5-CA with a Single Integer LO-PLL in 14nm CMOS FinFET. - Barosaim Sung; Hyun-Gi Seok; Jaekwon Kim; Jaehoon Lee 005; Taejin Jang; Ilhoon Jang; Youngmin Kim; Anna Yu; Jong-Hyun Jang; Jiyoung Lee; Jeongyeol Bae; Euiyoung Park; et al. (ISSCC, 2022)

A 0.56mW 63.6dB SNDR 250MS/s SAR ADC in 8nm FinFET. - Jaehoon Lee 005; Yong Lim; Jongmi Lee; Taejin Jang; Kwonwoo Kang; Jongpil Cho; Seunghyun Oh; Jongwoo Lee (VLSI Technology and Circuits, 2022)

A Sparse DAE Solver in Maple. - Taejin Jang; Maitri Uppaluri; Venkat R. Subramanian 001 (CoRR, 2022)

A Single Path Digital-IF Receiver Supporting Inter/Intra 5-CA With a Single Integer LO-PLL in 14-nm CMOS FinFET. - Barosaim Sung; Hyun-Gi Seok; Jaekwon Kim; Jaehoon Lee 005; Taejin Jang; Ilhoon Jang; Youngmin Kim; Anna Yu; Jong-Hyun Jang; Jiyoung Lee; Jeongyeol Bae; Euiyoung Park; et al. (IEEE J. Solid State Circuits, 2022)

A Sparse Differential Algebraic Equation (DAE) and Stiff Ordinary Differential Equation (ODE) Solver in Maple. - Taejin Jang; Maitri Uppaluri; Kyeongjun Seo; Venkatasailanathan Ramadesigan; Venkat R. Subramanian 001 (Maple Trans., 2023)

A 0.036mm2 80Mb/s-to-15.96Gb/s C-PHY and D-PHY Combo Receiver with Background Calibrations in 4nm FinFET. - Woongki Min; Soo-Min Lee; Taejin Jang; Yunsik Jo; Hyoungjoong Kim; Younggyun Oh; Myeong-Cheol Kim; Hyeonji Han; Cheolhwan Lim; Seungjun Lee; Jihoon Lee; Yon Jun Shin; et al. (A-SSCC, 2024)