Implementation Issues of A Wideband Multi-Resolution Spectrum Sensing (MRSS) Technique for Cognitlve Radio (CR) Systems. - Jongmin Park; Youngsik Hur; Taejoong Song; Kwan-Woo Kim; Jungsuk Lee; Kyutae Lim; Chang-Ho Lee; Haksun Kim; Joy Laskar (CrownCom, 2006)

A Cross-layer Cognitive Radio Testbed for the Evaluation of Spectrum Sensing Receiver and Interference Analysis. - Jongmin Park; Kwan-Woo Kim; Taejoong Song; Sang Min Lee; Joonhoi Hur; Kyutae Lim; Joy Laskar (CrownCom, 2008)

A Fully-Integrated UHF Receiver with Multi-Resolution Spectrum-Sensing (MRSS) Functionality for IEEE 802.22 Cognitive-Radio Applications. - Jongmin Park; Taejoong Song; Joonhoi Hur; Sang Min Lee; Jungki Choi; Kihong Kim; Jungsuk Lee; Kyutae Lim; Chang-Ho Lee; Haksun Kim; Joy Laskar (ISSCC, 2008)

A Fully Integrated UHF-Band CMOS Receiver With Multi-Resolution Spectrum Sensing (MRSS) Functionality for IEEE 802.22 Cognitive Radio Applications. - Jongmin Park; Taejoong Song; Joonhoi Hur; Sang Min Lee; Jungki Choi; Kihong Kim; Kyutae Lim; Chang-Ho Lee; Haksun Kim; Joy Laskar (IEEE J. Solid State Circuits, 2009)

Subthreshold current mode matrix determinant computation for analog signal processing. - Stephen T. Kim; Jaehyouk Choi; Sungho Beck; Taejoong Song; Kyutae Lim; Joy Laskar (ISCAS, 2010)

A 122-mW Low-Power Multiresolution Spectrum-Sensing IC With Self-Deactivated Partial Swing Techniques. - Taejoong Song; Jongmin Park; Sang Min Lee; Jaehyouk Choi; Kihong Kim; Chang-Ho Lee; Kyutae Lim; Joy Laskar (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

Low-Power Technique for SRAM-Based On-Chip Arbitrary-Waveform Generator. - Taejoong Song; Sang Min Lee; Jongmin Park; Joonhoi Hur; Michael Lee 003; Kihong Kim; Chang-Ho Lee; Franklin Bien; Kyutae Lim; Joy Laskar (IEEE Trans. Instrum. Meas., 2011)

A 0.65V embedded SDRAM with smart boosting and power management in a 45nm CMOS technology. - Suk-Soo Pyo; Jun-Sung Kim; Jung-Han Kim; Hyun-Taek Jung; Taejoong Song; Cheol-Ha Lee; Gyun-Hong Kim; Young-Keun Lee; Kee Sup Kim (CICC, 2012)

Pseudo NMOS based sense amplifier for high speed single-ended SRAM. - Hanwool Jeong; Taewon Kim; Seong-Ook Jung; Taejoong Song; Gyu-Hong Kim (ICECS, 2014)

13.2 A 14nm FinFET 128Mb 6T SRAM with VMIN-enhancement techniques for low-power applications. - Taejoong Song; Woojin Rim; Jonghoon Jung; Giyong Yang; Jaeho Park; Sunghyun Park 003; Kang-Hyun Baek; Sanghoon Baek; Sang-Kyu Oh; Jinsuk Jung; Sungbong Kim; Gyu-Hong Kim; et al. (ISSCC, 2014)

A 14 nm FinFET 128 Mb SRAM With VMIN Enhancement Techniques for Low-Power Applications. - Taejoong Song; Woojin Rim; Jonghoon Jung; Giyong Yang; Jaeho Park; Sunghyun Park 003; Yongho Kim; Kang-Hyun Baek; Sanghoon Baek; Sang-Kyu Oh; Jinsuk Jung; Sungbong Kim; et al. (IEEE J. Solid State Circuits, 2015)

Switching pMOS Sense Amplifier for High-Density Low-Voltage Single-Ended SRAM. - Hanwool Jeong; Taewon Kim; Kyoman Kang; Taejoong Song; Gyu-Hong Kim; Hyo-Sig Won; Seong-Ook Jung (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

Offset-Compensated Cross-Coupled PFET Bit-Line Conditioning and Selective Negative Bit-Line Write Assist for High-Density Low-Power SRAM. - Hanwool Jeong; Taewon Kim; Younghwi Yang; Taejoong Song; Gyu-Hong Kim; Hyo-Sig Won; Seong-Ook Jung (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

Trip-Point Bit-Line Precharge Sensing Scheme for Single-Ended SRAM. - Hanwool Jeong; Taewon Kim; Taejoong Song; Gyu-Hong Kim; Seong-Ook Jung (IEEE Trans. Very Large Scale Integr. Syst., 2015)

17.1 A 10nm FinFET 128Mb SRAM with assist adjustment system for power, performance, and area optimization. - Taejoong Song; Woojin Rim; Sunghyun Park 003; Yongho Kim; Jonghoon Jung; Giyong Yang; Sanghoon Baek; Jaeseung Choi 001; Bongjae Kwon; Yunwoo Lee; Sungbong Kim; Gyu-Hong Kim; et al. (ISSCC, 2016)

Bitline Precharging and Preamplifying Switching pMOS for High-Speed Low-Power SRAM. - Hanwool Jeong; Juhyun Park; Tae Woo Oh; Woojin Rim; Taejoong Song; Gyu-Hong Kim; Hyo-Sig Won; Seong-Ook Jung (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

28-nm 1T-1MTJ 8Mb 64 I/O STT-MRAM with symmetric 3-section reference structure and cross-coupled sensing amplifier. - Artur Antonyan; Suk-Soo Pyo; Hyuntaek Jung; Gwanhyeob Koh; Taejoong Song (ISCAS, 2017)

12.2 A 7nm FinFET SRAM macro using EUV lithography for peripheral repair analysis. - Taejoong Song; Hoonki Kim; Woojin Rim; Yongho Kim; Sunghyun Park 003; Changnam Park; Minsun Hong; Giyong Yang; Jeongho Do; Jinyoung Lim; Seungyoung Lee; Ingyum Kim; et al. (ISSCC, 2017)

A 10 nm FinFET 128 Mb SRAM With Assist Adjustment System for Power, Performance, and Area Optimization. - Taejoong Song; Woojin Rim; Sunghyun Park 003; Yongho Kim; Giyong Yang; Hoonki Kim; Sanghoon Baek; Jonghoon Jung; Bongjae Kwon; Sungwee Cho; Hyuntaek Jung; Yongjae Choo; et al. (IEEE J. Solid State Circuits, 2017)

Embedded MRAM Macro for eFlash Replacement. - Artur Antonyan; Suk-Soo Pyo; Hyuntaek Jung; Taejoong Song (ISCAS, 2018)

A 7nm FinFET SRAM using EUV lithography with dual write-driver-assist circuitry for low-voltage applications. - Taejoong Song; Jonghoon Jung; Woojin Rim; Hoonki Kim; Yongho Kim; Changnam Park; Jeongho Do; Sunghyun Park 003; Sungwee Cho; Hyuntaek Jung; Bongjae Kwon; Hyun-Su Choi; et al. (ISSCC, 2018)

Half-and-Half Compare Content Addressable Memory with Charge-Sharing Based Selective Match-Line Precharge Scheme. - Woong Choi; Jongsun Park 001; Hoonki Kim; Changnam Park; Taejoong Song (VLSI Circuits, 2018)

A Voltage and Temperature Tracking SRAM Assist Supporting 740mV Dual-Rail Offset for Low-Power and High-Performance Applications in 7nm EUV FinFET Technology. - Inhak Lee; Hanwool Jeong; Sangyeop Baeck; Siddharth Gupta 008; Changnam Park; Dongwook Seo; Jaeseung Choi 001; Jaeyoung Kim; Hoon Kim; Jungmyung Kang; Sunyung Jang; Daeyoung Moon; et al. (ISSCC, 2019)

Bitline Charge-Recycling SRAM Write Assist Circuitry for $V_{ mathrm{MIN}}$ Improvement and Energy Saving. - Hanwool Jeong; Se Hyeok Oh; Tae Woo Oh; Hoonki Kim; Changnam Park; Woojin Rim; Taejoong Song; Seong-Ook Jung (IEEE J. Solid State Circuits, 2019)

Design Rule Evaluation Framework Using Automatic Cell Layout Generator for Design Technology Co-Optimization. - Kyeongrok Jo; Seyong Ahn; Jungho Do; Taejoong Song; Taewhan Kim 001; Kyu-Myung Choi (IEEE Trans. Very Large Scale Integr. Syst., 2019)

A 14.7Mb/mm2 28nm FDSOI STT-MRAM with Current Starved Read Path, 52Ω/Sigma Offset Voltage Sense Amplifier and Fully Trimmable CTAT Reference. - El Mehdi Boujamaa; Samsudeen Mohamed Ali; Steve Ngueya Wandji; Alexandra Gourio; Suk-Soo Pyo; Gwanhyeob Koh; Yoonjong Song; Taejoong Song; Jongwook Kye; Jean-Christophe Vial; Andrew Sowden; Manuj Rathor; et al. (VLSI Circuits, 2020)

An Embedded Level-Shifting Dual-Rail SRAM for High-Speed and Low-Power Cache. - Tae Hyun Kim; Hanwool Jeong; Juhyun Park; Hoonki Kim; Taejoong Song; Seong-Ook Jung (IEEE Access, 2020)

24.3 A 3nm Gate-All-Around SRAM Featuring an Adaptive Dual-BL and an Adaptive Cell-Power Assist Circuit. - Taejoong Song; Woojin Rim; Hoonki Kim; Keun Hwi Cho; Taeyeong Kim; Taejung Lee; Geumjong Bae; Dong-Won Kim; S. D. Kwon; Sanghoon Baek; Jonghoon Jung; Jongwook Kye; et al. (ISSCC, 2021)

5nm Low Power SRAM Featuring Dual-Rail Architecture with Voltage-Tracking Assist Circuit for 5G mobile application. - Sangyeop Baeck; Inhak Lee; Hoyoung Tang; Dongwook Seo; Jaeseung Choi 001; Taejoong Song; Jongwook Kye (VLSI Circuits, 2021)

SRAM Write- and Performance-Assist Cells for Reducing Interconnect Resistance Effects Increased with Technology Scaling. - Keonhee Cho; Heekyung Choi; In Jun Jung; Ji Sang Oh; Tae Woo Oh; Ki-Ryong Kim; Giseok Kim; Taemin Choi; Changsoo Sim; Taejoong Song; Seong-Ook Jung (VLSI Circuits, 2021)

A 28nm Embedded Flash Memory with 100MHz Read Operation and 7.42Mb/mm2 at 0.85V featuring for Automotive Application. - Hyunjin Shin; Myeonghee Oh; Jaeseung Choi 001; Taejoong Song; Jongwook Kye (VLSI Circuits, 2021)

A Wide-Range Static Current-Free Current Mirror-Based LS With Logic Error Detection for Near-Threshold Operation. - Hanwool Jeong; Tae Hyun Kim; Changnam Park; Hoonki Kim; Taejoong Song; Seong-Ook Jung (IEEE J. Solid State Circuits, 2021)

3nm Gate-All-Around (GAA) Design-Technology Co-Optimization (DTCO) for succeeding PPA by Technology. - Taejoong Song; Hakchul Jung; Giyoung Yang; Hoyoung Tang; Hayoung Kim; Dongwook Seo; Hoonki Kim; Woojin Rim; Sanghoon Baek; Sangyeop Baeck; Jonghoon Jung (CICC, 2022)

A 14-nm Low Voltage SRAM with Charge-Recycling and Charge Self-Saving Techniques for Low-Power Applications. - Keonhee Cho; Giseok Kim; Ji Sang Oh; Ki-Ryong Kim; Changsu Sim; Younmee Bae; Mijung Kim; Sangyeop Baeck; Taejoong Song; Seong-Ook Jung (VLSI Technology and Circuits, 2022)

Standard Cell Design Optimization with Advanced MOL Technology in 3nm GAA Process. - Giyoung Yang; Hakchul Jung; Jinyoung Lim; Jaewoo Seo; Ingyum Kim; Jisu Yu; Hyeoungyu You; Jeongsoon Kong; Garoom Kim; Minjae Jeong; Chanhee Park; Sera An; et al. (VLSI Technology and Circuits, 2022)

SRAM Write- and Performance-Assist Cells for Reducing Interconnect Resistance Effects Increased With Technology Scaling. - Keonhee Cho; Heekyung Choi; In Jun Jung; Ji Sang Oh; Tae Woo Oh; Ki-Ryong Kim; Giseok Kim; Taemin Choi; Changsu Sim; Taejoong Song; Seong-Ook Jung (IEEE J. Solid State Circuits, 2022)

A 3-nm Gate-All-Around SRAM Featuring an Adaptive Dual-Bitline and an Adaptive Cell-Power Assist Circuit. - Taejoong Song; Hoonki Kim; Woojin Rim; Hakchul Jung; Changnam Park; Inhak Lee; Sanghoon Baek; Jonghoon Jung (IEEE J. Solid State Circuits, 2022)

A Contention-Free Wordline Supporting Circuit for High Wordline Resistance in Sub-10-nm SRAM Designs. - Tae-Hyun Kim; Juhyun Park; In Jun Jung; Hoonki Kim; Taejoong Song; Seong-Ook Jung (IEEE Trans. Circuits Syst. II Express Briefs, 2024)