A high-speed adaptive linear equalizer with ISI level detection using periodic training pattern. - Jin-Cheol Seo; Tae-Ho Kim; Taek-Joon An; Kwan Yoon; Jin-Ku Kang (ISOCC, 2012)

A 1.62/2.7/5.4Gbps clock and data recovery circuit for DisplayPort 1.2. - Jin-Cheol Seo; Sang-Soon Im; Kwan-Hee Yoon; Seung-Wook Oh; Taek-Joon An; Gi-Yeol Bae; Jin-Ku Kang (SoCC, 2012)

A 8.7mW 5-Gb/s clock and data recovery circuit with 0.18-µm CMOS. - Taek-Joon An; Kyung-Sub Son; Young-Jin Kim; In-Seok Kong; Jin-Ku Kang (ISCAS, 2014)

A burst-mode clock and data recovery circuit with two symmetric quadrature VCO's. - Bum-Hee Choi; Kyung-Sub Son; Taek-Joon An; Jin-Ku Kang (IEICE Electron. Express, 2016)

Design of a third-order delta-sigma TDC with error-feedback structure. - Seong-Mun An; Kyung-Sub Son; Taek-Joon An; Jin-Ku Kang (IEICE Electron. Express, 2019)

Eye-open monitor using two-dimensional counter value profile. - Kyung-Sub Son; Yong-Hwan Moon; Sanghun Baek; Namyong Kim; Taek-Joon An; Jin-Ku Kang (IEICE Electron. Express, 2019)

A 0.42-3.45 Gb/s Referenceless Clock and Data Recovery Circuit With Counter-Based Unrestricted Frequency Acquisition. - Kyung-Sub Son; Taek-Joon An; Yong-Hwan Moon; Jin-Ku Kang (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

A 0.32-2.7 Gb/s Reference-Less Continuous-Rate Clock and Data Recovery Circuit With Unrestricted and Fast Frequency Acquisition. - Nguyen Huu Tho; Ho-Joon Lee; Taek-Joon An; Jin-Ku Kang (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

An Overhead-Reduced Key Coding Technique for High-Speed Serial Interface. - Jaepil Bak; Taek-Joon An; Youngwoo Kim; Jin-Ku Kang (IEEE Access, 2022)