Area minimization algorithm for parallel prefix adders under bitwise delay constraints. - Taeko Matsunaga; Yusuke Matsunaga (ACM Great Lakes Symposium on VLSI, 2007)

Timing-Constrained Area Minimization Algorithm for Parallel Prefix Adders. - Taeko Matsunaga; Yusuke Matsunaga (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

Synthesis of parallel prefix adders considering switching activities. - Taeko Matsunaga; Shinji Kimura; Yusuke Matsunaga (ICCD, 2008)

Framework for Parallel Prefix Adder Synthesis Considering Switching Activities. - Taeko Matsunaga; Shinji Kimura; Yusuke Matsunaga (IPSJ Trans. Syst. LSI Des. Methodol., 2009)

Multi-operand adder synthesis on FPGAs using generalized parallel counters. - Taeko Matsunaga; Shinji Kimura; Yusuke Matsunaga (ASP-DAC, 2010)

Power and delay aware synthesis of multi-operand adders targeting LUT-based FPGAs. - Taeko Matsunaga; Shinji Kimura; Yusuke Matsunaga (ISLPED, 2011)

Multi-Operand Adder Synthesis Targeting FPGAs. - Taeko Matsunaga; Shinji Kimura; Yusuke Matsunaga (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011)

An Exact Approach for GPC-Based Compressor Tree Synthesis. - Taeko Matsunaga; Shinji Kimura; Yusuke Matsunaga (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)