A 500-MS/s 8-bit SAR ADC Generated from an Automated Layout Generation Framework in 14-nm FinFET Technology. - Yunseong Jo; Taeseung Kang; Jeonghyu Yang; Jaeduk Han (ASP-DAC, 2025)

Process-Portable Layout Generation of High-Speed Digital Circuit Using Standard Cells in FinFET. - Taeseung Kang; Taeho Shin; Heejun Kim; Jaeduk Han (SMACD, 2025)

A 96-Gb/s 1.6-Vppd PAM-8 Transmitter With High-Swing and Low-Loading Cascaded Driver in 40-nm CMOS Technology. - Taeseung Kang; Jeonghyu Yang; Eunji Song; Seungwoo Son; Hyuntae Kim; Jaeduk Han (IEEE Trans. Very Large Scale Integr. Syst., 2025)