A Scheduling Algorithm for Conditional Resource Sharing. - Taewhan Kim 001; Jane W.-S. Liu; C. L. Liu 001 (ICCAD, 1991)

Utilization of Multiport Memories in Data Path Synthesis. - Taewhan Kim 001; C. L. Liu 001 (DAC, 1993)

Register allocation for data flow graphs with conditional branches and loops. - Chaeryung Park; Taewhan Kim 001; C. L. Liu 001 (EURO-DAC, 1993)

A Stepwise Refinement Data Path Synthesis Procedure for Easy Testability. - Taewhan Kim 001; Ki-Seok Chung; Chien-Liang Liu (EDAC-ETC-EUROASIC, 1994)

A scheduling algorithm for conditional resource sharing-a hierarchical reduction approach. - Taewhan Kim 001; Noritake Yonezawa; Jane W.-S. Liu; C. L. Liu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994)

A new approach to the multiport memory allocation problem in data path synthesis. - Taewhan Kim 001; C. L. Liu 001 (Integr., 1995)

An integrated algorithm for incremental data path synthesis. - Taewhan Kim 001; C. L. Liu 001 (J. VLSI Signal Process., 1996)

Arithmetic Optimization Using Carry-Save-Adders. - Taewhan Kim 001; William Jao; Steven W. K. Tjiang (DAC, 1998)

Circuit optimization using carry-save-adder cells. - Taewhan Kim 001; William Jao; Steven W. K. Tjiang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)

Register Allocation - A Hierarchical Reduction Approach. - Chaeryung Park; Taewhan Kim 001; C. L. Liu 001 (J. VLSI Signal Process., 1998)

Optimal allocation of carry-save-adders in arithmetic optimization. - Junhyung Um; Taewhan Kim 001; C. L. Liu 001 (ICCAD, 1999)

A timing-driven synthesis of arithmetic circuits using carry-save-adders (short paper). - Taewhan Kim 001; Junhyung Um (ASP-DAC, 2000)

A fine-grained arithmetic optimization technique for high-performance/low-power data path synthesis. - Junhyung Um; Taewhan Kim 001; C. L. Liu 001 (DAC, 2000)

Behavioral-level partitioning for low power design in control-dominated application. - Ki-Seok Chung; Taewhan Kim 001; Chien-Liang Liu (ACM Great Lakes Symposium on VLSI, 2000)

Decomposition of Bus-Invert Coding for Low-Power I/O. - Sungpack Hong; Taewhan Kim 001; Unni Narayanan; Ki-Seok Chung (J. Circuits Syst. Comput., 2000)

An Accurate Exploration of Timing and Area Trade-Offs in Arithmetic Optimization Using Carry-Save-Adders. - Youngtae Kim; Taewhan Kim 001 (J. Circuits Syst. Comput., 2000)

A practical approach to the synthesis of arithmetic circuits usingcarry-save-adders. - Taewhan Kim 001; Junhyung Um (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

An Integrated Approach to Data Path Synthesis for Behavioral-level Power Optimization. - Chaeryung Park; Taewhan Kim 001; C. L. Liu 001 (VLSI Design, 2000)

Accurate exploration of timing and area trade-offs in arithmetic optimization using carry-save-adders. - Youngtae Kim; Taewhan Kim 001 (ASP-DAC, 2001)

A Static Estimation Technique of Power Sensitivity in Logic Circuits. - Taewhan Kim 001; Ki-Seok Chung; Chien-Liang Liu (DAC, 2001)

An accurate evaluation of routing density for symmetrical FPGAs. - Nak-Woong Eum; Taewhan Kim 001; Chong-Min Kyung (ACM Great Lakes Symposium on VLSI, 2001)

A Router for Symmetrical FPGAs Based on Exact Routing Density Evaluation. - Nak-Woong Eum; Taewhan Kim 001; Chong-Min Kyung (ICCAD, 2001)

An Integrated Data Path Optimization for Low Power Based on Network Flow Method. - Chun-Gi Lyuh; Taewhan Kim 001; Chien-Liang Liu (ICCAD, 2001)

An Optimal Allocation of Carry-Save-Adders in Arithmetic Circuits. - Junhyung Um; Taewhan Kim 001 (IEEE Trans. Computers, 2001)

G-vector: A New Model for Glitch Analysis in Logic Circuits. - Ki-Seok Chung; Taewhan Kim 001; C. L. Liu 001 (J. VLSI Signal Process., 2001)

Address assignment combined with scheduling in DSP code generation. - Yoonseo Choi; Taewhan Kim 001 (DAC, 2002)

Layout-aware synthesis of arithmetic circuits. - Junhyung Um; Taewhan Kim 001 (DAC, 2002)

Coupling-aware high-level interconnect synthesis for low power. - Chun-Gi Lyuh; Taewhan Kim 001; Ki-Wook Kim (ICCAD, 2002)

Layout-driven resource sharing in high-level synthesis. - Junhyung Um; Jae-Hoon Kim 001; Taewhan Kim 001 (ICCAD, 2002)

An efficient low-power binding algorithm in high-level synthesis. - Yoonseo Choi; Taewhan Kim 001 (ISCAS (4), 2002)

Address code optimization using code scheduling for digital signal processors. - Yoonseo Choi; Taewhan Kim 001 (ISCAS (5), 2002)

Enhanced bus invert encodings for low-power. - Unni Narayanan; Ki-Seok Chung; Taewhan Kim 001 (ISCAS (5), 2002)

Binding Algorithm for Power Optimization Based on Network Flow Method. - Yoonseo Choi; Taewhan Kim 001 (J. Circuits Syst. Comput., 2002)

A Complete Model for Glitch Analysis in Logic Circuits. - Ki-Seok Chung; Taewhan Kim 001; C. L. Liu 001 (J. Circuits Syst. Comput., 2002)

Domino logic synthesis based on implication graph. - Ki-Wook Kim; Taewhan Kim 001; C. L. Liu 001; Sung-Mo Kang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

Logic transformation for low-power synthesis. - Ki-Wook Kim; Taewhan Kim 001; TingTing Hwang; Sung-Mo Kang; C. L. Liu 001 (ACM Trans. Design Autom. Electr. Syst., 2002)

Synthesis and Optimization of Combinational Interface Circuits. - Ki-Seok Chung; Rajesh K. Gupta 001; Taewhan Kim 001; C. L. Liu 001 (J. VLSI Signal Process., 2002)

Memory layout techniques for variables utilizing efficient DRAM access modes in embedded system design. - Yoonseo Choi; Taewhan Kim 001 (DAC, 2003)

Code Placement with Selective Cache Activity Minimization for Embedded Real-time Software Design. - Junhyung Um; Taewhan Kim 001 (ICCAD, 2003)

An efficient inverse multiplier/divider architecture for cryptography systems. - Junhyung Um; Sangwoo Lee; Youngsoo Park; Sungik Jun; Taewhan Kim 001 (ISCAS (5), 2003)

Address assignment in DSP code generation - an integrated approach. - Yoonseo Choi; Taewhan Kim 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

Synthesis of arithmetic circuits considering layout effects. - Junhyung Um; Taewhan Kim 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

Minimum delay optimization for domino circuits - a coupling-aware approach. - Ki-Wook Kim; Seong-Ook Jung; Taewhan Kim 001; Sung-Mo Kang (ACM Trans. Design Autom. Electr. Syst., 2003)

Coupling delay optimization by temporal decorrelation using dual threshold voltage technique. - Ki-Wook Kim; Seong-Ook Jung; Taewhan Kim 001; Prashant Saxena; C. L. Liu 001; S.-M. S. Kang (IEEE Trans. Very Large Scale Integr. Syst., 2003)

High-level synthesis for low power based on network flow method. - Chun-Gi Lyuh; Taewhan Kim 001 (IEEE Trans. Very Large Scale Integr. Syst., 2003)

Resource-constrained low-power bus encoding with crosstalk delay elimination. - Meeyoung Cha; Chun-Gi Lyuh; Taewhan Kim 001 (ASP-DAC, 2004)

An integrated approach to timing-driven synthesis and placement of arithmetic circuits. - Keoncheol Shin; Taewhan Kim 001 (ASP-DAC, 2004)

Memory access scheduling and binding considering energy minimization in multi-bank memory systems. - Chun-Gi Lyuh; Taewhan Kim 001 (DAC, 2004)

Profile-based optimal intra-task voltage scheduling for hard real-time applications. - Jaewon Seo; Taewhan Kim 001; Ki-Seok Chung (DAC, 2004)

Leakage power minimization for the synthesis of parallel multiplier circuits. - Keoncheol Shin; Taewhan Kim 001 (ACM Great Lakes Symposium on VLSI, 2004)

CeRA: A Router for Symmetrical FPGAs Based on Exact Routing Density Evaluation. - Nak-Woong Eum; Taewhan Kim 001; Chong-Min Kyung (IEEE Trans. Computers, 2004)

Coupling-aware high-level interconnect synthesis [IC layout]. - Chun-Gi Lyuh; Taewhan Kim 001; Ki-Wook Kim (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Tight integration of timing-driven synthesis and placement of parallel multiplier circuits. - Keoncheol Shin; Taewhan Kim 001 (IEEE Trans. Very Large Scale Integr. Syst., 2004)

Memory access optimization through combined code scheduling, memory allocation, and array binding in embedded system design. - Jungeun Kim; Taewhan Kim 001 (DAC, 2005)

Memory layout techniques for variables utilizing efficient DRAM access modes in embedded system design. - Yoonseo Choi; Taewhan Kim 001; Hwansoo Han (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Thermal-aware high-level synthesis based on network flow method. - Pilok Lim; Taewhan Kim 001 (CODES+ISSS, 2006)

A systematic IP and bus subsystem modeling for platform-based system design. - Junhyung Um; Woo-Cheol Kwon; Sungpack Hong; Young-Taek Kim; Kyu-Myung Choi; Jeong-Taek Kong; Soo-Kwan Eo; Taewhan Kim 001 (DATE, 2006)

HW/SW partitioning techniques for multi-mode multi-task embedded applications. - Young-Jun Kim 002; Taewhan Kim 001 (ACM Great Lakes Symposium on VLSI, 2006)

Application-Driven Low-Power Techniques Using Dynamic Voltage Scaling. - Taewhan Kim 001 (RTCSA, 2006)

Memory Access Driven Storage Assignment for Variables in Embedded System Design. - Yoonseo Choi; Taewhan Kim 001 (J. Circuits Syst. Comput., 2006)

A HW/SW Partitioner for Multi-Mode Multi-Task Embedded Applications. - Young-Jun Kim 002; Taewhan Kim 001 (J. VLSI Signal Process., 2006)

Resource Sharing Combined with Layout Effects in High-Level Synthesis. - Junhyung Um; Taewhan Kim 001 (J. VLSI Signal Process., 2006)

Integration of Code Scheduling, Memory Allocation, and Array Binding for Memory-Access Optimization. - Taewhan Kim 001; Jungeun Kim (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Simultaneous clock buffer sizing and polarity assignment for power/ground noise minimization. - Hochang Jang; Taewhan Kim 001 (DAC, 2009)

Thermal-Aware High-Level Synthesis Based on Network Flow Method. - Pilok Lim; Ki-Seok Chung; Taewhan Kim 001 (J. Circuits Syst. Comput., 2009)

Thermal sensor allocation and placement for reconfigurable systems. - Byunghyun Lee; Ki-Seok Chung; Bontae Koo; Nak-Woong Eum; Taewhan Kim 001 (ACM Trans. Design Autom. Electr. Syst., 2009)

Clock tree embedding for 3D ICs. - Tak-Yung Kim; Taewhan Kim 001 (ASP-DAC, 2010)

Clock tree synthesis with pre-bond testability for 3D stacked IC designs. - Tak-Yung Kim; Taewhan Kim 001 (DAC, 2010)

Bounded skew clock routing for 3D stacked IC designs: Enabling trade-offs between power and clock skew. - Tak-Yung Kim; Taewhan Kim 001 (Green Computing Conference, 2010)

Task-Level Dynamic Voltage Scaling for Embedded System Design: Recent Theoretical Results. - Taewhan Kim 001 (J. Comput. Sci. Eng., 2010)

WaveMin: a fine-grained clock buffer polarity assignment combined with buffer sizing. - Deokjin Joo; Taewhan Kim 001 (DAC, 2011)

Clock design techniques considering circuit reliability. - YongHwan Kim; Minseok Kang; Kyoung-Hwan Lim; Sangdo Park; Deokjin Joo; Taewhan Kim 001 (ISOCC, 2011)

Buffer Sizing and Polarity Assignment in Clock Tree Synthesis for Power/Ground Noise Minimization. - Hochang Jang; Deokjin Joo; Taewhan Kim 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

Clock Tree synthesis for TSV-based 3D IC designs. - Tak-Yung Kim; Taewhan Kim 001 (ACM Trans. Design Autom. Electr. Syst., 2011)

Design Methodologies for Reliable Clock Networks. - Deokjin Joo; Minseok Kang; Taewhan Kim 001 (J. Comput. Sci. Eng., 2012)

Synthesis of Adaptable Hybrid Adders for Area Optimization under Timing Constraint. - YongHwan Kim; Sanghoon Kwak; Taewhan Kim 001 (ACM Trans. Design Autom. Electr. Syst., 2012)

Power Saving by Task-Level Dynamic Voltage Scaling. - Taewhan Kim 001 (Handbook of Energy-Aware and Green Computing, 2012)

An optimal algorithm of adjustable delay buffer insertion for solving clock skew variation problem. - Juyeon Kim; Deokjin Joo; Taewhan Kim 001 (DAC, 2013)

Comprehensive technique for designing and synthesizing TSV fault-tolerant 3D clock trees. - Heechun Park; Taewhan Kim 001 (ICCAD, 2013)

Tutorial: Methodology for designing reliable clock networks. - Taewhan Kim 001 (SoCC, 2013)

Resource Allocation and Design Techniques of Prebond Testable 3-D Clock Tree. - Tak-Yung Kim; Taewhan Kim 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

An Optimal Allocation Algorithm of Adjustable Delay Buffers and Practical Extensions for Clock Skew Optimization in Multiple Power Mode Designs. - Kyoung-Hwan Lim; Deokjin Joo; Taewhan Kim 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Mixed allocation of adjustable delay buffers combined with buffer sizing in clock tree synthesis of multiple power mode designs. - Kitae Park; Geunho Kim 002; Taewhan Kim 001 (DATE, 2014)

A Fine-Grained Clock Buffer Polarity Assignment for High-Speed and Low-Power Digital Systems. - Deokjin Joo; Taewhan Kim 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Integrated Resource Allocation and Binding in Clock Mesh Synthesis. - Minseok Kang; Taewhan Kim 001 (ACM Trans. Design Autom. Electr. Syst., 2014)

Synthesis of resonant clock networks supporting dynamic voltage / frequency scaling. - Seyong Ahn; Minseok Kang; Marios C. Papaefthymiou; Taewhan Kim 001 (ASP-DAC, 2015)

Synthesis for Power-Aware Clock Spines. - Hyungjung Seo; Juyeon Kim; Minseok Kang; Taewhan Kim 001 (ICCAD, 2015)

Clock skew optimization for maximizing time margin by utilizing flexible flip-flop timing. - Hyungjung Seo; Jeongwoo Heo; Taewhan Kim 001 (ISQED, 2015)

Synthesis of TSV Fault-Tolerant 3-D Clock Trees. - Heechun Park; Taewhan Kim 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Clock buffer polarity assignment utilizing useful clock skews for power noise reduction. - Deokjin Joo; Taewhan Kim 001 (ASP-DAC, 2016)

Allocation of multi-bit flip-flops in logic synthesis for power optimization. - Dongyoun Yi; Taewhan Kim 001 (ICCAD, 2016)

Timing Analysis and Optimization Based on Flexible Flip-Flop Timing Model. - Jeongwoo Heo; Taewhan Kim 001 (ISVLSI, 2016)

Synthesizing Asynchronous Circuits toward Practical Use. - Heechun Park; Taewhan Kim 001 (ISVLSI, 2016)

Optimal utilization of adjustable delay clock buffers for timing correction in designs with multiple power modes. - Juyeon Kim; Deokjin Joo; Taewhan Kim 001 (Integr., 2016)

Design Methodology for Synthesizing Resonant Clock Networks in the Presence of Dynamic Voltage/Frequency Scaling. - Seyong Ahn; Minseok Kang; Marios C. Papaefthymiou; Taewhan Kim 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

Clock buffer polarity assignment under useful skew constraints. - Deokjin Joo; Taewhan Kim 001 (Integr., 2017)

Adjustable Delay Buffer Allocation under Useful Clock Skew Scheduling. - Juyeon Kim; Taewhan Kim 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Cohesive techniques for cell layout optimization supporting 2D metal-1 routing completion. - Kyeongrok Jo; Seyong Ahn; Taewhan Kim 001; Kyu-Myung Choi (ASP-DAC, 2018)

Structure optimizations of neuromorphic computing architectures for deep neural network. - Heechun Park; Taewhan Kim 001 (DATE, 2018)

Design and algorithm for clock gating and flip-flop co-optimization. - Giyoung Yang; Taewhan Kim 001 (ICCAD, 2018)

SRAM On-Chip Monitoring Methodology for Energy Efficient Memory Operation at Near Threshold Voltage. - Taehwan Kim 007; Kwangok Jeong; Taewhan Kim 001; Kyu-Myung Choi (ISVLSI, 2019)

Hybrid asynchronous circuit generation amenable to conventional EDA flow. - Heechun Park; Taewhan Kim 001 (Integr., 2019)

Design Rule Evaluation Framework Using Automatic Cell Layout Generator for Design Technology Co-Optimization. - Kyeongrok Jo; Seyong Ahn; Jungho Do; Taejoong Song; Taewhan Kim 001; Kyu-Myung Choi (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Synthesis of Hardware Performance Monitoring and Prediction Flow Adapting to Near-Threshold Computing and Advanced Process Nodes. - Jeongwoo Heo; Kwangok Jeong; Taewhan Kim 001; Kyu-Myung Choi (ASP-DAC, 2020)

Lightening Asynchronous Pipeline Controller Through Resynthesis and Optimization. - Jeongwoo Heo; Taewhan Kim 001 (ASP-DAC, 2020)

Steady state driven power gating for lightening always-on state retention storage. - Taehwan Kim 007; Gyoung-Hwan Hyun; Taewhan Kim 001 (ISLPED, 2020)

SRAM on-chip monitoring methodology for high yield and energy efficient memory operation at near threshold voltage. - Taehwan Kim 007; Kwangok Jeong; Jungyun Choi; Taewhan Kim 001; Kyu-Myung Choi (Integr., 2020)

Boosting Pin Accessibility Through Cell Layout Topology Diversification. - Suwan Kim; Kyeongrok Jo; Taewhan Kim 001 (ASP-DAC, 2021)

Speeding up MUX-FSM based Stochastic Computing for On-device Neural Networks. - Jongsung Kang; Taewhan Kim 001 (DATE, 2021)

Simultaneous Transistor Folding and Placement in Standard Cell Layout Synthesis. - Kyeonghyeon Baek; Taewhan Kim 001 (ICCAD, 2021)

Optimal Transistor Placement Combined with Global In-cell Routing in Standard Cell Layout Synthesis. - Kyeongrok Jo; Taewhan Kim 001 (ICCD, 2021)

Challenges on DTCO Methodology Towards Deep Submicron Interconnect Technology. - Heechun Park; Kyungjoon Chang; Jooyeon Jeong; Jaehoon Ahn; Ki-Seok Chung; Taewhan Kim 001 (ISOCC, 2021)

Analyses of Power Staple Inserting Methodologies for Mitigating IR-Drops. - Jaejoon Yoon; Sehyeon Chung; Taewhan Kim 001 (ISOCC, 2021)

Minimally Allocating Always-on State Retention Storage for Supporting Power Gating Circuits. - Soomin Kim 001; Taewhan Kim 001 (ISQED, 2021)

Utilizing Middle-of-Line Resource in Filler Cells for Fixing Routing Failures. - Jooyeon Jeong; Taewhan Kim 001 (MWSCAS, 2021)

Minimum Implant Area-Aware Threshold Voltage Refinement in Pre-Placement. - Eunsol Jeong; Heechun Park; Jooyeon Jeong; Taewhan Kim 001 (MWSCAS, 2021)

Practical Approach to Cell Replacement for Resolving Pin Inaccessibility. - Suwan Kim; Taewhan Kim 001 (MWSCAS, 2021)

Common Kernels and Convolutions in Binary- and Ternary-Weight Neural Networks. - Byungmin Ahn; Taewhan Kim 001 (J. Circuits Syst. Comput., 2021)

Allocation of Multibit Retention Flip-Flops for Power Gated Circuits: Algorithm-Design Unified Approach. - Gyoung-Hwan Hyun; Taewhan Kim 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

Reusable Delay Path Synthesis for Lightening Asynchronous Pipeline Controller. - Jeongwoo Heo; Taewhan Kim 001 (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Allocation of Always-On State Retention Storage for Power Gated Circuits - Steady-State- Driven Approach. - Taehwan Kim 007; Heechun Park; Taewhan Kim 001 (IEEE Trans. Very Large Scale Integr. Syst., 2021)

A Systematic Removal of Minimum Implant Area Violations under Timing Constraint. - Eunsol Jeong; Heechun Park; Taewhan Kim 001 (DATE, 2022)

Pin Accessibility-driven Placement Optimization with Accurate and Comprehensive Prediction Model. - Suwan Kim; Taewhan Kim 001 (DATE, 2022)

Pin Accessibility and Routing Congestion Aware DRC Hotspot Prediction Using Graph Neural Network and U-Net. - Kyeonghyeon Baek; Hyunbum Park; Suwan Kim; Kyumyung Choi; Taewhan Kim 001 (ICCAD, 2022)

Design and Technology Co-Optimization Utilizing Multi-Bit Flip-Flop Cells. - Soomin Kim 001; Taewhan Kim 001 (ICCAD, 2022)

Optimizing Timing in Placement Through I/O Signal Flipping on Multi-bit Flip-flops. - Soomin Kim 001; Taewhan Kim 001 (ISCAS, 2022)

Selective Clock Gating Based on Comprehensive Power Saving Analysis. - Sora Park; Taewhan Kim 001 (ISCAS, 2022)

Improving Pin Accessibility of Standard Cells Through Fin Depopulation. - Doyeon Won; Taewhan Kim 001 (ISCAS, 2022)

Improving Performance and Power by Co-Optimizing Middle-of-Line Routing, Pin Pattern Generation, and Contact over Active Gates in Standard Cell Layout Synthesis. - Sehyeon Chung; Jooyeon Jeong; Taewhan Kim 001 (ISLPED, 2022)

Tightly Linking 3D Via Allocation Towards Routing Optimization for Monolithic 3D ICs. - Suwan Kim; Sehyeon Chung; Taewhan Kim 001; Heechun Park (ISLPED, 2022)

Analysis of Impacting Multi-stack Standard Cells on Chip Implementation. - Kyungjoon Chang; Taewhan Kim 001 (ISOCC, 2022)

ECO routing based on network flow method. - Sehyeon Chung; Taewhan Kim 001 (Integr., 2022)

Speeding-up neuromorphic computation for neural networks: Structure optimization approach. - Heechun Park; Taewhan Kim 001 (Integr., 2022)

Deeper Weight Pruning Without Accuracy Loss in Deep Neural Networks: Signed-Digit Representation-Based Approach. - Byungmin Ahn; Taewhan Kim 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Hardware Performance Monitoring Methodology at Near-Threshold Computing and Advanced Technology Nodes: From Design to Postsilicon. - Jeongwoo Heo; Kwangok Jeong; Jungyun Choi; Taewhan Kim 001; Kyumyung Choi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

DTOC: integrating Deep-learning driven Timing Optimization into the state-of-the-art Commercial EDA tool. - Kyungjoon Chang; Jaehoon Ahn; Heechun Park; Kyu-Myung Choi; Taewhan Kim 001 (DATE, 2023)

Synthesis and Utilization of Standard Cells Amenable to Gear Ratio of Gate-Metal Pitches for Improving Pin Accessibility. - Jooyeon Jeong; Sehyeon Chung; Kyeongrok Jo; Taewhan Kim 001 (DATE, 2023)

Placement Legalization Amenable to Mixed-cell-height Standard Cells Integrating into State-of-the-art Commercial EDA Tool. - Hwapyong Kim; Taewhan Kim 001 (ACM Great Lakes Symposium on VLSI, 2023)

Design and Technology Co-Optimization for Useful Skew Scheduling on Multi-Bit Flip-Flops. - Suwan Kim; Taewhan Kim 001 (ICCAD, 2023)

Machine Learning Based Flip-Flop Grouping for Toggling Driven Clock Gating. - Sora Park; Taewhan Kim 001 (ISCAS, 2023)

Machine Learning Driven Synthesis of Clock Gating. - Doyeon Won; Soomin Kim 001; Taewhan Kim 001 (ISLPED, 2023)

Optimizing Timing for Multi-bit Flip-Flop Intensive Designs Compatible with Commercial EDA Flow. - Ilseon Ha; Taewhan Kim 001 (ISOCC, 2023)

Fast Refinement on Placement Legalization for Designs with Mixed-Height Cells. - Kihwan Jeon; Taewhan Kim 001 (ISOCC, 2023)

Allocation of Multi-bit Flip-Flops Targeting Low-Power Chips. - Jinmyoung Kim; Taewhan Kim 001 (ISOCC, 2023)

Maximizing Power Saving Through State-Driven Clock Gating. - Chaehyun Kim; Taewhan Kim 001 (ISOCC, 2023)

Challenges on Design and Technology Co-Optimization: Design Automation Perspective. - Taewhan Kim 001 (MWSCAS, 2023)

Debanking Techniques on Multi-bit Flip-flops for Reinforcing Useful Clock Skew Scheduling. - Jaewan Yang; Taewhan Kim 001 (SOCC, 2023)

Eliminating Minimum Implant Area Violations With Design Quality Preservation. - Eunsol Jeong; Taewhan Kim 001; Heechun Park (IEEE Trans. Very Large Scale Integr. Syst., 2023)

Binding Multi-bit Flip-flop Cells through Design and Technology Co-optimization. - Jooyeon Jeong; Taewhan Kim 001 (DAC, 2024)

Optimal Transistor Folding and Placement for Synthesizing Standard Cells of Complementary FET Technology. - Suwan Kim; Taewhan Kim 001 (DAC, 2024)

Standard Cell Layout Generator Amenable to Design Technology Co-Optimization in Advanced Process Nodes. - Handong Cho; Hyunbae Seo; Sehyeon Chung; Kyu-Myung Choi; Taewhan Kim 001 (DATE, 2024)

BOXGB: Design Parameter Optimization with Systematic Integration of Bayesian Optimization and XGBoost. - Chanhee Jeon; Doyeon Won; Jaewan Yang; Kyu-Myung Choi; Taewhan Kim 001 (DATE, 2024)

Optimal Layout Synthesis of Multi-Row Standard Cells for Advanced Technology Nodes. - Sehyeon Chung; Hyunbae Seo; Handong Cho; Kyumyung Choi; Taewhan Kim 001 (ICCAD, 2024)

Net Topology Exploration and Tuning for Mitigating Congestion in Global Routing. - Hwapyong Kim; Taewhan Kim 001 (ISCAS, 2024)

Methodology of Resolving Design Rule Checking Violations Coupled with Fully Compatible Prediction Model. - Suwan Kim; Hyunbum Park; Kyeonghyeon Baek; Kyumyung Choi; Taewhan Kim 001 (ISPD, 2024)

Recent Research in Design and Technology Co-Optimization with Multi-Bit Flip-Flops. - Taewhan Kim 001 (MWSCAS, 2024)

Design and Allocation of Multi-bit Flip-flop Cells Amenable to Placement Legalization in Physical Design. - Yeongyeong Shin; Taewhan Kim 001 (SOCC, 2024)

Improving Timing Quality Through Net Topology Optimization in Global Routing. - Jayoung Yang; Taewhan Kim 001 (SOCC, 2024)

Pre-route timing prediction and optimization with graph neural network models. - Kyungjoon Chang; Taewhan Kim 001 (Integr., 2024)

Placement legalization for heterogeneous cells of non-integer multiple-heights. - Jooyeon Jeong; Taewhan Kim 001 (Integr., 2024)

CSyn-fp: Standard Cell Synthesis of Advanced Nodes With Simultaneous Transistor Folding and Placement. - Kyeonghyeon Baek; Taewhan Kim 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Enhancing Design Qualities Utilizing Multibit Flip-Flops: A Design and Technology Co-Optimization Driven Approach. - Soomin Kim; Taewhan Kim 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Recap of the 29th Edition of the Asia and South Pacific Design Automation Conference (ASPDAC 2024). - Taewhan Kim 001 (IEEE Des. Test, 2024)

DTOC-P: Deep-Learning-Driven Timing Optimization Using Commercial EDA Tool With Practicality Enhancement. - Jaehoon Ahn; Kyungjoon Chang; Kyumyung Choi; Taewhan Kim 001; Heechun Park (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Pin Accessibility and Routing Congestion Aware DRC Hotspot Prediction for Designs in Advanced Technology Nodes With Consolidated Practical Applicability and Sustainability. - Hyunbum Park; Kyeonghyeon Baek; Suwan Kim; Kyumyung Choi; Taewhan Kim 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

PPA-Aware Tier Partitioning for 3D IC Placement with ILP Formulation. - Eunsol Jeong; Taewhan Kim 001; Heechun Park (ASP-DAC, 2025)

Invited: Physical Design Challenges for Design Technology Co-optimization. - Taewhan Kim 001 (ISPD, 2025)

Design and Utilization of Multiskewed Multibit Flip-Flop Cells for Timing Optimization: Design and Technology Co-Optimization Approach. - Suwan Kim; Taewhan Kim 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)