Fast validation of DRAM protocols with timed petri nets. - Matthias Jung 001; Kira Kraft; Taha Soliman; Chirag Sudarshan; Christian Weis; Norbert Wehn (MEMSYS, 2019)

Efficient FeFET Crossbar Accelerator for Binary Neural Networks. - Taha Soliman; Ricardo Olivo; Tobias Kirchner; Cecilia De la Parra; Maximilian Lederer; Thomas Kämpfe; Andre Guntoro; Norbert Wehn (ASAP, 2020)

Enhancing the Utilization of Dot-Product Engines in Deep Learning Accelerators. - Taha Soliman; Armin Runge; Leonardo Ecco (IPDPS Workshops, 2020)

A Ferroelectric FET Based In-memory Architecture for Multi-Precision Neural Networks. - Taha Soliman; Ricardo Olivo; Tobias Kirchner; Maximilian Lederer; Thomas Kämpfe; Andre Guntoro; Norbert Wehn (SoCC, 2020)

Adaptable Approximation Based on Bit Decomposition for Deep Neural Network Accelerators. - Taha Soliman; Cecilia De la Parra; Andre Guntoro; Norbert Wehn (AICAS, 2021)

A Novel DRAM-Based Process-in-Memory Architecture and its Implementation for CNNs. - Chirag Sudarshan; Taha Soliman; Cecilia De la Parra; Christian Weis; Leonardo Ecco; Matthias Jung 001; Norbert Wehn; Andre Guntoro (ASP-DAC, 2021)

Exploiting Resiliency for Kernel-Wise CNN Approximation Enabled by Adaptive Hardware Design. - Cecilia De la Parra; Ahmed El-Yamany; Taha Soliman; Akash Kumar 001; Norbert Wehn; Andre Guntoro (ISCAS, 2021)

Efficient Hardware Approximation for Bit-Decomposition Based Deep Neural Network Accelerators. - Taha Soliman; Amro Eldebiky; Cecilia De la Parra; Andre Guntoro; Norbert Wehn (SOCC, 2022)

FeFET versus DRAM based PIM Architectures: A Comparative Study. - Chirag Sudarshan; Taha Soliman; Thomas Kämpfe; Christian Weis; Norbert Wehn (VLSI-SoC, 2022)

A Weighted Current Summation Based Mixed Signal DRAM-PIM Architecture for Deep Neural Network Inference. - Chirag Sudarshan; Taha Soliman; Jan Lappas; Christian Weis; Mohammad Hassani Sadi; Matthias Jung 001; Andre Guntoro; Norbert Wehn (IEEE J. Emerg. Sel. Topics Circuits Syst., 2022)

Increasing Throughput of In-Memory DNN Accelerators by Flexible Layerwise DNN Approximation. - Cecilia De la Parra; Taha Soliman; Andre Guntoro; Akash Kumar 001; Norbert Wehn (IEEE Micro, 2022)

Ultra-low power approximate processing-in-memory acceleration for deep neural networks = Approximative Prozessierung viellagiger neuronaler Netze in Speichermatrizen für Systeme mit ultra-geringer Leistungsaufnahme. - Taha Soliman (2022)

FELIX: A Ferroelectric FET Based Low Power Mixed-Signal In-Memory Architecture for DNN Acceleration. - Taha Soliman; Nellie Laleni; Tobias Kirchner; Franz Müller 001; Ashish Shrivastava; Thomas Kämpfe; Andre Guntoro; Norbert Wehn (ACM Trans. Embed. Comput. Syst., 2022)

Simulation-driven Latency Estimations for Multi-core Machine Learning Accelerators. - Yannick Braatz; Dennis Sebastian Rieber; Taha Soliman; Oliver Bringmann 001 (AICAS, 2023)

SimPyler: A Compiler-Based Simulation Framework for Machine Learning Accelerators. - Yannick Braatz; Dennis Sebastian Rieber; Taha Soliman; Oliver Bringmann 001 (ASAP, 2023)

Torwards Variability Immune Scalable FeFET-based Macros for IMC DNN Accelerators. - Nellie Laleni; Taha Soliman; Cecilia De la Parra; Franz Müller 001; Tobias Kirchner; Andre Guntoro; Thomas Kämpfe; Norbert Wehn; T. Jang (ICECS, 2023)

Demonstration of Differential Mode Ferroelectric Field-Effect Transistor Array-Based in-Memory Computing Macro for Realizing Multiprecision Mixed-Signal Artificial Intelligence Accelerator. - Vivek Parmar; Franz Müller 001; Jing-Hua Hsuen; Sandeep Kaur Kingra; Nellie Laleni; Yannick Raffel; Maximilian Lederer; Alptekin Vardar; Konrad Seidel; Taha Soliman; Tobias Kirchner; Tarek Ali; et al. (Adv. Intell. Syst., 2023)

CoNAX: Towards Comprehensive Co-Design Neural Architecture Search Using HW Abstractions. - Yannick Braatz; Taha Soliman; Shubham Rai; Dennis Sebastian Rieber; Oliver Bringmann 001 (ASAP, 2024)

Error Detection and Correction Codes for Safe In-Memory Computations. - Luca Parrini; Taha Soliman; Benjamin Hettwer; Jan Micha Borrmann; Simranjeet Singh; Ankit Bende; Vikas Rana; Farhad Merchant; Norbert Wehn (ETS, 2024)

AIO: An Abstraction for Performance Analysis Across Diverse Accelerator Architectures. - Joseph Rogers; Taha Soliman; Magnus Jahre (ISCA, 2024)

Accelerating Automated Driving and ADAS Using HW/SW Codesign. - Shubham Rai; Cecilia De la Parra; Martin Rapp; Jan Micha Borrmann; Nina Bretz; Stefan Metzlaff; Taha Soliman; Christoph Schorn (SOCC, 2024)

Neoscope: How Resilient Is My SoC to Workload Churn? - Joseph Rogers; Lieven Eeckhout; Taha Soliman; Magnus Jahre (ISCA, 2025)