A multiword based high speed ECC scheme for low-voltage embedded SRAMS. - Shah M. Jahinuzzaman; Tahseen Shakir; Sumanjit Lubana; Jaspal Singh Shah; Manoj Sachdev (ESSCIRC, 2008)

A word-line boost driver design for low operating voltage 6T-SRAMs. - Tahseen Shakir; Manoj Sachdev (MWSCAS, 2012)

A read-assist write-back voltage sense amplifier for low voltage-operated SRAMs. - Tahseen Shakir; Manoj Sachdev (SoCC, 2012)

A body-bias based current sense amplifier for high-speed low-power embedded SRAMs. - Tahseen Shakir; Manoj Sachdev (SoCC, 2014)

7.3 A 224Gb/s 3pJ/b 40dB Insertion Loss Transceiver in 3nm FinFET CMOS. - Dirk Pfaff; Muhammad Nummer; Noman Hai; Peter Xia; Kai Ge Yang; Mohammad-Mahdi Mohsenpour; Marc-Andre LaCroix; Babak Zamanlooy; Tom Eeckelaert; Dmitry Petrov; Mostafa Haroun; Carson R. Dick; et al. (ISSCC, 2024)

A 224Gb/s 3pJ/bit 42dB Insertion Loss Post-FEC Error Free Transceiver in 3-nm FinFET CMOS (Invited). - Dirk Pfaff; Muhammad Nummer; Noman Hai; Jingjing Xia 001; Kai Ge Yang; Mohammad-Mahdi Mohsenpour; Choon-Haw CH Leong; Marc-Andre LaCroix; Babak Zamanlooy; Tom Eeckelaert; Dmitry Petrov; Mostafa Haroun; et al. (CICC, 2025)

A 224 Gb/s 3 pJ/bit 40 dB Insertion Loss Transceiver in 3-nm FinFET CMOS. - Dirk Pfaff; Muhammad Nummer; Noman Hai; Jingjing Xia 001; Kai Ge Yang; Mohammad-Mahdi Mohsenpour; Choon-Haw C. H. Leong; Marc-Andre LaCroix; Babak Zamanlooy; Tom Eeckelaert; Dmitry Petrov; Mostafa Haroun; et al. (IEEE J. Solid State Circuits, 2025)