Theoretical Studies of Electronic Transport in Gallium-Arsenide Material and Devices Using an Ensemble Monte Carlo Method (Modeling) - Tahui Wang (1986)

Device and circuit simulation of anomalous DX trap effects in DCFL and SCFL HEMT inverters. - Tahui Wang; Sheng-Jyh Wu; Chimoon Huang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

Copper interconnect electromigration behaviors in various structures and lifetime improvement by cap/dielectric interface treatment. - M. H. Lin; Y. L. Lin; K. P. Chang; K. C. Su; Tahui Wang (Microelectron. Reliab., 2005)

Effects of width scaling and layout variation on dual damascene copper interconnect electromigration. - M. H. Lin; K. P. Chang; K. C. Su; Tahui Wang (Microelectron. Reliab., 2007)

Effects of length scaling on electromigration in dual-damascene copper interconnects. - M. H. Lin; M. T. Lin; Tahui Wang (Microelectron. Reliab., 2008)

Chip-level characterization and RTN-induced error mitigation beyond 20nm floating gate flash memory. - T. W. Lin; S. H. Ku; C. H. Cheng; C. W. Lee; Ijen Huang; Wen-Jer Tsai; T. C. Lu; W. P. Lu; K. C. Chen; Tahui Wang; Chih-Yuan Lu (IRPS, 2018)

Investigation of data pattern effects on nitride charge lateral migration in a charge trap flash memory by using a random telegraph signal method. - Y. H. Liu; H. Y. Lin; C. M. Jiang; Tahui Wang; W. J. Tsai; T. C. Lu; K. C. Chen; Chih-Yuan Lu (IRPS, 2018)

Correlation between SET-state current level and read-disturb failure time in a resistive switching memory. - P. C. Su; C. M. Jiang; C. W. Wang; Tahui Wang (IRPS, 2018)

Interfacial-Layer Design for Hf1-xZrxO2-Based FTJ Devices: From Atom to Array. - H.-L. Chiang; J.-F. Wang; K.-H. Lin; C.-H. Nien; J.-J. Wu; Kuo-Yu Hsiang; C.-P. Chuu; Y.-W. Chen; X. W. Zhang; C. W. Liu; Tahui Wang; C. C. Wang; et al. (VLSI Technology and Circuits, 2022)