Performance Optimization By Wire and Buffer Sizing Under The Transmission Line Model. - Tai-Chen Chen; Song-Ra Pan; Yao-Wen Chang (ICCD, 2001)

Timing modeling and optimization under the transmission line model. - Tai-Chen Chen; Song-Ra Pan; Yao-Wen Chang (IEEE Trans. Very Large Scale Integr. Syst., 2004)

Multilevel full-chip gridless routing considering optical proximity correction. - Tai-Chen Chen; Yao-Wen Chang (ASP-DAC, 2005)

A novel framework for multilevel full-chip gridless routing. - Tai-Chen Chen; Yao-Wen Chang; Shyh-Chang Lin (ASP-DAC, 2006)

Recent Research and Emerging Challenges in Physical Design for Manufacturability/Reliability. - Chung-Wei Lin; Ming-Chao Tsai; Kuang-Yao Lee; Tai-Chen Chen; Ting-Chi Wang; Yao-Wen Chang (ASP-DAC, 2007)

Multilevel Full-Chip Gridless Routing With Applications to Optical-Proximity Correction. - Tai-Chen Chen; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Predictive Formulae for OPC With Applications to Lithography-Friendly Routing. - Tai-Chen Chen; Guang-Wan Liao; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

ILP-based inter-die routing for 3D ICs. - Chia-Jen Chang; Pao-Jen Huang; Tai-Chen Chen; Chien-Nan Jimmy Liu (ASP-DAC, 2011)

Micro-bump assignment for 3D ICs using order relation. - Ta-Yu Kuan; Yi-Chun Chang; Tai-Chen Chen (ASP-DAC, 2012)

Escape routing of differential pairs considering length matching. - Tai-Hung Li; Wan-Chun Chen; Xian-Ting Cai; Tai-Chen Chen (ASP-DAC, 2012)

Native-conflict-avoiding track routing for double patterning technology. - Bi-Ting Lai; Tai-Hung Li; Tai-Chen Chen (SoCC, 2012)

LASER: layout-aware analog synthesis environment on laker. - Yu-Ching Liao; Yen-Lung Chen; Xian-Ting Cai; Chien-Nan Jimmy Liu; Tai-Chen Chen (ACM Great Lakes Symposium on VLSI, 2013)

Electromigration- and obstacle-avoiding routing tree construction. - Yun-Chih Tsai; Tai-Hung Li; Tai-Chen Chen; Chung-Wei Yeh (VLSI-DAT, 2013)

Design-for-debug routing for FIB probing. - Chia-Yi Lee; Tai-Hung Li; Tai-Chen Chen (DATE, 2014)

The overview of 2014 CAD contest at ICCAD. - Iris Hui-Ru Jiang; Natarajan Viswanathan; Tai-Chen Chen; Jin-Fu Li 001 (ICCAD, 2014)

Automatic Floorplanning for AI SoCs. - Tai-Chen Chen; Pei-Yu Lee; Tung-Chieh Chen (VLSI-DAT, 2020)

Flexible chip placement via reinforcement learning: late breaking results. - Fu-Chieh Chang 001; Yu-Wei Tseng; Ya-Wen Yu; Ssu-Rui Lee; Alexandru Cioba; I-Lun Tseng; Da-Shan Shiu; Jhih-Wei Hsu; Cheng-Yuan Wang; Chien-Yi Yang; Ren-Chu Wang; Yao-Wen Chang; et al. (DAC, 2022)

Flexible Multiple-Objective Reinforcement Learning for Chip Placement. - Fu-Chieh Chang 001; Yu-Wei Tseng; Ya-Wen Yu; Ssu-Rui Lee; Alexandru Cioba; I-Lun Tseng; Da-Shan Shiu; Jhih-Wei Hsu; Cheng-Yuan Wang; Chien-Yi Yang; Ren-Chu Wang; Yao-Wen Chang; et al. (CoRR, 2022)

Modern Fixed-Outline Floorplanning with Rectilinear Soft Modules. - Yu-Yang Chen; Yi-Chen Lin; Tzu-Han Hsu; Iris Hui-Ru Jiang; Tung-Chieh Chen; Tai-Chen Chen; Hua-Yu Chang (ICCAD, 2024)