A 4-tap 125-MHz mixed-signal echo canceller for Gigabit Ethernet on copper wire. - Tai-Cheng Lee; Behzad Razavi (CICC, 2000)

A 125-MHz CMOS mixed-signal equalizer for Gigabit Ethernet on copper wire. - Tai-Cheng Lee; Behzad Razavi (CICC, 2001)

A 125-MHz mixed-signal echo canceller for Gigabit Ethernet on copper wire. - Tai-Cheng Lee; Behzad Razavi (IEEE J. Solid State Circuits, 2001)

CMOS 2.4-GHz receiver front end with area-efficient inductors and digitally calibrated 90° delay network. - Chih-Chun Tang; Chia-Hsin Wu; Kun-Hsien Li; Tai-Cheng Lee; Shen-Iuan Liu (ISCAS (3), 2002)

A stabilization technique for phase-locked frequency synthesizers. - Tai-Cheng Lee; Behzad Razavi (IEEE J. Solid State Circuits, 2003)

A 10 Gbase-LX4 receiver front end transimpedance amplifier and limiting amplifier. - Hung-Chieh Tsai; Jyh-Yih Yeh; Wei-Hsuan Tu; Tai-Cheng Lee; Chorng-Kuang Wang (ISCAS (4), 2004)

An optimization technique for RF buffers with active inductors. - Tai-Cheng Lee; Yen-Chuan Huang (ISCAS (4), 2005)

A linear-approximation technique for digitally-calibrated pipelined A/D converters. - Ding-Lan Shen; Tai-Cheng Lee (ISCAS (2), 2005)

A Spur Suppression Technique for Phase-Locked Frequency Synthesizers. - Tai-Cheng Lee; Wei-Liang Lee (ISSCC, 2006)

The design and analysis of a DLL-based frequency synthesizer for UWB application. - Tai-Cheng Lee; Keng-Jan Hsiao (IEEE J. Solid State Circuits, 2006)

The design and analysis of a Miller-divider-based clock generator for MBOA-UWB application. - Tai-Cheng Lee; Yen-Chuan Huang (IEEE J. Solid State Circuits, 2006)

A mixed-signal GFSK demodulator for Bluetooth. - Tai-Cheng Lee; Chin-Chi Chen (IEEE Trans. Circuits Syst. II Express Briefs, 2006)

A Delay-Line-Based GFSK Demodulator for Low-IF Receivers. - Hong-Sing Kao; Ming-Jen Yang; Tai-Cheng Lee (ISSCC, 2007)

A 6-bit 800-MS/s Pipelined A/D Converter With Open-Loop Amplifiers. - Ding-Lan Shen; Tai-Cheng Lee (IEEE J. Solid State Circuits, 2007)

A Low-Jitter 8-to-10GHz Distributed DLL for Multiple-Phase Clock Generation. - Keng-Jan Hsiao; Tai-Cheng Lee (ISSCC, 2008)

The Design and Analysis of a Fully Integrated Multiplying DLL With Adaptive Current Tuning. - Keng-Jan Hsiao; Tai-Cheng Lee (IEEE J. Solid State Circuits, 2008)

An 8-GHz to 10-GHz Distributed DLL for Multiphase Clock Generation. - Keng-Jan Hsiao; Tai-Cheng Lee (IEEE J. Solid State Circuits, 2009)

A Split-Based Digital Background Calibration Technique in Pipelined ADCs. - Li-Han Hung; Tai-Cheng Lee (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

An all-digital de-skew clock generator for arbitrary wide range delay. - Kevin Fong; Yu-Cheng Hung; Zuow-Zun Chen; Tai-Cheng Lee (APCCAS, 2010)

An offset phase-locked loop spread spectrum clock generator for SATA III. - Chin-Yu Lin; Chun-Yu Chiang; Tai-Cheng Lee (CICC, 2010)

A 10b 100MS/s 4.5mW pipelined ADC with a time sharing technique. - Yen-Chuan Huang; Tai-Cheng Lee (ISSCC, 2010)

A 0.02-mm 2 9-Bit 50-MS/s Cyclic ADC in 90-nm Digital CMOS Technology. - Yen-Chuan Huang; Tai-Cheng Lee (IEEE J. Solid State Circuits, 2010)

Nonlinear R-2R Transistor-Only DAC. - Tai-Cheng Lee; Cheng-Hsiao Lin (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

The Design and Analysis of Dual-Delay-Path Ring Oscillators. - Zuow-Zun Chen; Tai-Cheng Lee (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

The Study of a Dual-Mode Ring Oscillator. - Zuow-Zun Chen; Tai-Cheng Lee (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

A 10-bit 100-MS/s 4.5-mW Pipelined ADC With a Time-Sharing Technique. - Yen-Chuan Huang; Tai-Cheng Lee (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

A 10-bit 200-MS/s reconfigurable pipelined A/D converter. - Chia-Chi Ho; Tai-Cheng Lee (VLSI-DAT, 2012)

Analysis of the leakage effect in a pipelined ADC with nanoscale CMOS technologies. - Chin-Yu Lin; Yen-Chuan Huang; Tai-Cheng Lee (VLSI-DAT, 2013)

Jitter error cancellation technique in digital domain for ADC. - Chin-Yu Lin; Tai-Cheng Lee (VLSI-DAT, 2013)

A 6-GHz Self-Oscillating Spread-Spectrum Clock Generator. - Chien-Heng Wong; Tai-Cheng Lee (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

A 6-Gb/s adaptive-loop-bandwidth clock and data recovery (CDR) circuit. - Li-Hung Chiueh; Tai-Cheng Lee (A-SSCC, 2014)

A 20-MHz BW 75-dB SFDR shifted-averaging VCO-based ΔΣ modulator. - Yu-Hsuan Kang; Chin-Yu Lin; Tai-Cheng Lee (ISCAS, 2014)

A compact multi-input thermoelectric energy harvesting system with 58.5% power conversion efficiency and 32.4-mW output power capability. - Chia-Lun Chang; Tai-Cheng Lee (ISIC, 2014)

21.2 A 2.3GHz fractional-N dividerless phase-locked loop with -112dBc/Hz in-band phase noise. - Po-Chun Huang; Wei-Sung Chang; Tai-Cheng Lee (ISSCC, 2014)

A 3X-oversampling hybrid clock and data recovery circuit with programmable bandwidth. - Jia-An Jheng; Wei-Sung Chang; Tai-Cheng Lee (VLSI-DAT, 2014)

A 12-bit 210-MS/s 5.3-mW pipelined-SAR ADC with a passive residue transfer technique. - Chin-Yu Lin; Tai-Cheng Lee (VLSIC, 2014)

A Fractional-N Divider-Less Phase-Locked Loop With a Subsampling Phase Detector. - Wei-Sung Chang; Po-Chun Huang; Tai-Cheng Lee (IEEE J. Solid State Circuits, 2014)

2.4-GHz High-Efficiency Adaptive Power. - Cheng-Jyun Li; Tai-Cheng Lee (IEEE Trans. Very Large Scale Integr. Syst., 2014)

A single-channel 10-b 400-MS/s 8.7-mW pipeline ADC in a 90-nm technology. - Chen-Kai Hsu; Tai-Cheng Lee (A-SSCC, 2015)

A 84.7-DR wide BW incremental ADC using CT structure. - Ting-Yang Wang; Tai-Cheng Lee (VLSI-DAT, 2015)

A technique for in-band phase noise reduction in fractional-N frequency synthesizers. - Chun-Ping Wang; Tai-Cheng Lee (A-SSCC, 2016)

27.7 A 10b 2.6GS/s time-interleaved SAR ADC with background timing-skew calibration. - Chin-Yu Lin; Yen-Hsin Wei; Tai-Cheng Lee (ISSCC, 2016)

Session 15 overview: Oversampling data converters. - Venkatesh Srinivasan; Tai-Cheng Lee (ISSCC, 2016)

A Compact Multi-Input Power Conversion System with High Time-Efficiency Inductor-Sharing Technique for Thermoelectric Energy Harvesting Applications. - Chia-Lun Chang; Tai-Cheng Lee (J. Circuits Syst. Comput., 2016)

A 5 GHz Fractional-N ADC-Based Digital Phase-Locked Loops With -243.8 dB FOM. - Wei-Sung Chang; Tai-Cheng Lee (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

A 12-bit 210-MS/s 2-Times Interleaved Pipelined-SAR ADC With a Passive Residue Transfer Technique. - Chin-Yu Lin; Tai-Cheng Lee (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

A 200-MS/s Phase-Detector-Based Comparator With 400-μVrms Noise. - Chin-Yu Lin; Chien-Heng Wong; Chia-Hau Hsu; Yen-Hsin Wei; Tai-Cheng Lee (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

An energy-efficient self-charged crystal oscillator with a quadrature-phase shifter technique. - Wei-Sung Chang; Dai-En Jhou; Yu-Hong Yang; Tai-Cheng Lee (A-SSCC, 2017)

A 10-Gb/s equalizer with digital adaptation. - Jui-Cheng Hsiao; Dai-En Jhou; Tai-Cheng Lee (ISOCC, 2017)

Session 28 overview: Hybrid ADCs. - Tai-Cheng Lee; Bob Verbruggen; Un-Ku Moon (ISSCC, 2017)

Few-mode 850-nm VCSEL chip with direct 16-QAM OFDM encoding at 80-Gbit/s for 100-m OM4 MMF link. - Hsuan-Yun Kao; Cheng-Ting Tsai; Chun-Yen Pong; Shan-Fong Liang; Zu-Kai Weng; Yu-Chieh Chi; Hao-Chung Kuo; Jian Jang Huang; Tai-Cheng Lee; Tien-Tsorng Shih; Jau-Ji Jou; Wood-Hi Cheng; et al. (OFC, 2017)

F2: FinFETs & FDSOI - A mixed signal circuit designer's perspective. - Venkatesh Srinivasan; Stephane Le Tuai; Tai-Cheng Lee (ISSCC, 2018)

A 10-bit 2.6-GS/s Time-Interleaved SAR ADC With a Digital-Mixing Timing-Skew Calibration Technique. - Chin-Yu Lin; Yen-Hsin Wei; Tai-Cheng Lee (IEEE J. Solid State Circuits, 2018)

A SAR-Assisted Continuous-Time Incremental ΣΔ ADC With First-Order Noise Coupling. - Yu-Lun Hsieh; Tai-Cheng Lee (ASICON, 2019)

Incremental Timing-Driven Placement With Approximated Signoff Wire Delay and Regression-Based Cell Delay. - Tai-Cheng Lee; Yih-Lang Li (IEEE Trans. Very Large Scale Integr. Syst., 2019)

/TPlace: Machine Learning-Based Delay-Aware Transistor Placement for Standard Cell Synthesis. - Tai-Cheng Lee; Cheng-Yen Yang; Yih-Lang Li (ICCAD, 2020)

A 5 GHz Outer-Loop Phase Noise Filter with Delay-Sampling Technique. - Kun-Ruei Li; Wei-Sung Chang; Tai-Cheng Lee (ISCAS, 2020)

25.6 A 5.25GHz Subsampling PLL with a VCO-Phase-Noise Suppression Technique. - Hsiu-Hsien Ting; Tai-Cheng Lee (ISSCC, 2020)

Analysis and Design of a Self-Charged Crystal Oscillator with Pulse Regulating Feedback Loop. - Hsiang-Chun Cheng; Yu-Hong Yang; Tai-Cheng Lee (VLSI-DAT, 2020)

A Type-3 FMCW Radar Synthesizer with Wide Frequency Modulation Bandwidth. - Cheng-Tang Chen; Yu-Hong Yang; Tai-Cheng Lee (ISCAS, 2022)

A Reinforcement Learning Agent for Obstacle-Avoiding Rectilinear Steiner Tree Construction. - Po-Yan Chen; Bing-Ting Ke; Tai-Cheng Lee; I-Ching Tsai; Tai-Wei Kung; Li-Yi Lin; En-Cheng Liu; Yun-Chih Chang; Yih-Lang Li; Mango C.-T. Chao (ISPD, 2022)

Path-Based Pre-Routing Timing Prediction for Modern Very Large-Scale Integration Designs. - Li-Wei Chen; Yao-Nien Sui; Tai-Cheng Lee; Yih-Lang Li; Mango C.-T. Chao; I-Ching Tsai; Tai-Wei Kung; En-Cheng Liu; Yun-Chih Chang (ISQED, 2022)

An Asynchronous Zero-Crossing-Based Incremental Delta-Sigma Converter. - Yen-Po Lai; Hao-Hsuan Chang; Tai-Cheng Lee (VLSI-DAT, 2022)

A Single-Channel 1-GS/s 7.48-ENOB Parallel Conversion Pipelined SAR ADC With a Varactor-Based Residue Amplifier. - Hao-Hsuan Chang; Tung-Cheng Lin; Tai-Cheng Lee (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A 6.0-11.0 Gb/s Reference-Less Sub-Baud-Rate Linear CDR With Wide-Range Frequency Acquisition Technique. - Yu-Hong Yang; Mou Tzou; Tai-Cheng Lee (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A 0.9-V 50-MS/s 67.3-dB-SNDR SAR-ISDM ADC With an Oscillator-Based Integrator. - Yen-Chun Chan; Che-Wei Chang; Tai-Cheng Lee (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

An 800-MS/s 10b Pipelined ADC with Floating Ring Amplifiers. - Chao-Yen Hsu; Mu-Heng Pi; Tai-Cheng Lee (ISOCC, 2024)

A 511-μW 89-dB-SNDR Asynchronous SAR-ISDM ADC With Noise Shaping Dynamic Amplifier and Time-Domain Noise-Slicing Technique. - Hao-Hsuan Chang; Ci-Ren Chen; Tai-Cheng Lee (IEEE J. Solid State Circuits, 2024)

A Sub-Baud-Rate Wireline Receiver With One-Tap DFE. - Yu-Hong Yang; Tai-Cheng Lee (IEEE J. Solid State Circuits, 2024)

An 800-MS/s 8.2-ENOB TDC-Assisted Pipelined-SAR ADC With Parallel Conversion. - Shao-Yu Wang; Tai-Cheng Lee (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A Pipelined-SAR ADC with a Compensation-Free Two-Stage Amplifier. - Chun-Tse Su; Chao-Yen Hsu; Shih-Jie Huang; Tai-Cheng Lee (ISCAS, 2025)

A Calibration-Free 9.3-ENOB 1-GS/s Pipelined ADC With PVT-Insensitive Nested Ring Amplifiers. - Chao-Yen Hsu; Tai-Cheng Lee (IEEE Trans. Circuits Syst. II Express Briefs, 2025)