A 0.5V Real-Time Computational CMOS Image Sensor with Programmable Kernel for Always-On Feature Extraction. - Tzu-Hsiang Hsu; Yen-Kai Chen; Tai-Hsing Wen; Wei-Chen Wei; Yi-Ren Chen; Fu-Chun Chang; Ren-Shuo Liu; Chung-Chuan Lo; Kea-Tiong Tang; Meng-Fan Chang; Chih-Cheng Hsieh (A-SSCC, 2019)

Physically Tightly Coupled, Logically Loosely Coupled, Near-Memory BNN Accelerator (PTLL-BNN). - Yun-Chen Lo; Yu-Chun Kuo; Yun-Sheng Chang; Jian-Hao Huang; Jun-Shen Wu; Wen-Chien Ting; Tai-Hsing Wen; Ren-Shuo Liu (ESSCIRC, 2019)

Considerations Of Integrating Computing-In-Memory And Processing-In-Sensor Into Convolutional Neural Network Accelerators For Low-Power Edge Devices. - Kea-Tiong Tang; Wei-Chen Wei; Zuo-Wei Yeh; Tzu-Hsiang Hsu; Yen-Cheng Chiu; Cheng-Xin Xue; Yu-Chun Kuo; Tai-Hsing Wen; Mon-Shu Ho; Chung-Chuan Lo; Ren-Shuo Liu; Chih-Cheng Hsieh; et al. (VLSI Circuits, 2019)

15.5 A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips. - Xin Si; Yung-Ning Tu; Wei-Hsing Huang; Jian-Wei Su; Pei-Jung Lu; Jing-Hong Wang; Ta-Wei Liu; Ssu-Yen Wu; Ruhui Liu; Yen-Chi Chou; Zhixiao Zhang; Syuan-Hao Sie; et al. (ISSCC, 2020)

15.4 A 22nm 2Mb ReRAM Compute-in-Memory Macro with 121-28TOPS/W for Multibit MAC Computing for Tiny AI Edge Devices. - Cheng-Xin Xue; Tsung-Yuan Huang; Je-Syu Liu; Ting-Wei Chang; Hui-Yao Kao; Jing-Hong Wang; Ta-Wei Liu; Shih-Ying Wei; Sheng-Po Huang; Wei-Chen Wei; Yi-Ren Chen; Tzu-Hsiang Hsu; et al. (ISSCC, 2020)