Behavioral Synthesis Methodology for HDL-Based Specification and Validation. - David Knapp; Tai Ly; Don MacMillen; Ron Miller (DAC, 1995)

Scheduling Using Behavioral Templates. - Tai Ly; David Knapp; Ron Miller; Don MacMillen (DAC, 1995)

Scalable and low power LDPC decoder design using high level algorithmic synthesis. - Yang Sun 001; Joseph R. Cavallaro; Tai Ly (SoCC, 2009)

Rapid and high-level constraint-driven prototyping using lab VIEW FPGA. - Hojin Kee; Swapnil Mhaske; David Uliana; Adam Arnesen; Newton Petersen; Taylor L. Riché; Dustyn Blasig; Tai Ly (GlobalSIP, 2014)

A 2.48Gb/s FPGA-based QC-LDPC decoder: An algorithmic compiler implementation. - Swapnil Mhaske; David Uliana; Hojin Kee; Tai Ly; Ahsan Aziz; Predrag Spasojevic (Sarnoff Symposium, 2015)

High-Throughput FPGA-Based QC-LDPC Decoder Architecture. - Swapnil Mhaske; Hojin Kee; Tai Ly; Ahsan Aziz; Predrag Spasojevic (VTC Fall, 2015)

A 2.48Gb/s QC-LDPC Decoder Implementation on the NI USRP-2953R. - Swapnil Mhaske; David Uliana; Hojin Kee; Tai Ly; Ahsan Aziz; Predrag Spasojevic (CoRR, 2015)

FPGA-accelerated simulation of a hybrid-ARQ system using high level synthesis. - Swapnil Mhaske; Hojin Kee; Tai Ly; Predrag Spasojevic (Sarnoff Symposium, 2016)

FPGA-Based Channel Coding Architectures for 5G Wireless Using High-Level Synthesis. - Swapnil Mhaske; Hojin Kee; Tai Ly; Ahsan Aziz; Predrag Spasojevic (Int. J. Reconfigurable Comput., 2017)