Design techniques to improve the device write margin for MRAM-based cache memory. - Hongbin Sun 001; Chuanyin Liu; Nanning Zheng 001; Tai Min; Tong Zhang 002 (ACM Great Lakes Symposium on VLSI, 2011)

Hardware implementation of KLMS algorithm using FPGA. - Xiaowei Ren; Pengju Ren; Badong Chen; Tai Min; Nanning Zheng 001 (IJCNN, 2014)

Four point probe ramped voltage stress as an efficient method to understand breakdown of STT-MRAM MgO tunnel junctions. - Simon Van Beek; Koen Martens; Philippe Roussel; Gabriele Luca Donadio; Johan Swerts; Sofie Mertens; Gouri Sankar Kar; Tai Min; Guido Groeseneken (IRPS, 2015)

Exploring the use of volatile STT-RAM for energy efficient video processing. - Hengyu Zhao; Hongbin Sun 001; Qiang Yang; Tai Min; Nanning Zheng 001 (ISQED, 2016)

An 8Kb 40-nm 2T2MTJ STT-MRAM Design with 2.6ns Access Time and Time-Adjustable Writing Process. - Xianwu Hu; Dongyang Li; Yu Wang; Jiayun Feng; Zizhao Ma; Shaohao Wang; Tai Min; Xiaoyang Zeng; Yufeng Xie (ASICON, 2021)

Synaptic 1/f noise injection for overfitting suppression in hardware neural networks. - Yan Du; Wei Shao 006; Zheng Chai; Hanzhang Zhao; Qihui Diao; Yawei Gao; Xihui Yuan; Qiaoqiao Wang; Tao Li; Weidong Zhang 002; Jian Fu Zhang 001; Tai Min (Neuromorph. Comput. Eng., 2022)

Comprehensive Study of Electrode Effect in Metal/CuInP2S6/Metal Heterostructures. - Yong Dong; Chao An; Yongyi Wu; Zhen Zhang 069; Tao Li; Tai Min; Jinbo Yang; Xuegang Chen; Mingliang Tian (Symmetry, 2023)

A 3D MCAM architecture based on flash memory enabling binary neural network computing for edge AI. - Maoying Bai; Shuhao Wu; Hai Wang; Hua Wang; Yang Feng; Yueran Qi; Chengcheng Wang; Zheng Chai; Tai Min; Jixuan Wu; Xuepeng Zhan; Jiezhi Chen (Sci. China Inf. Sci., 2024)

A 40nm STT-MRAM Near-Memory Computing Macro for Memory-Augmented Neural Network Acceleration. - Hongrui Meng; Yajun Wu; Shengchao Zhou; Zizhao Ma; Tai Min; Shaohao Wang; Yufeng Xie (ISCAS, 2025)