Efficient path metric access for reducing interconnect overhead in Viterbi decoders. - Ming-Der Shieh; Tai-Ping Wang; Chien-Ming Wu; Chun-Ming Huang (ISCAS, 2006)

以文件分類技術預測股價趨勢 (Predicting Trends of Stock Prices with Text Classification Techniques) [In Chinese]. - Jiun-Da Chen; Tai-Ping Wang; Chao-Lin Liu (ROCLING, 2007)

Reducing Interconnect Complexity for Efficient Path Metric Memory Management in Viterbi Decoders. - Ming-Der Shieh; Tai-Ping Wang; Chien-Ming Wu (IEICE Trans. Inf. Syst., 2008)

Low-power register-exchange survivor memory architectures for Viterbi decoders. - Ming-Der Shieh; Tai-Ping Wang; Der-Wei Yang (IET Circuits Devices Syst., 2009)

Efficient nuclei segmentation based on spectral graph partitioning. - Gwo Giun Chris Lee; Shi-Yu Hung; Tai-Ping Wang; Chun-Fu (Richard) Chen; Chi-Kuang Sun; Yi-Hua Liao (ISCAS, 2016)

An Area-Efficient Scalable Test Module to Support Low Pin-Count Testing. - Tong-Yu Hsieh; Tai-Ping Wang; Shuo Yang; Chin-An Hsu; Yi-Lung Lin (IEICE Trans. Electron., 2016)

Complexity-Aware Gabor Filter Bank Architecture Using Principal Component Analysis. - Gwo Giun Chris Lee; Chun-Hsi Huang; Chun-Fu (Richard) Chen; Tai-Ping Wang (J. Signal Process. Syst., 2017)

Reconfigurable Edge via Analytics Architecture. - Shih-Yu Chen; Gwo Giun Chris Lee; Tai-Ping Wang; Chin-Wei Huang; Jia-Hong Chen; Chang-Ling Tsai (AICAS, 2019)