Novel Application of Deep Learning for Adaptive Testing Based on Long Short-Term Memory. - Tai Song; Huaguo Liang; Ying Sun; Zhengfeng Huang; Maoxiang Yi; Xiangsheng Fang; Aibin Yan (VTS, 2019)

Pattern Reorder for Test Cost Reduction Through Improved SVMRANK Algorithm. - Tai Song; Huaguo Liang; Tianming Ni; Zhengfeng Huang; Yingchun Lu; Jinlei Wan; Aibin Yan (IEEE Access, 2020)

Non-Intrusive Online Distributed Pulse Shrinking-Based Interconnect Testing in 2.5D IC. - Tianming Ni; Hao Chang; Tai Song; Qi Xu; Zhengfeng Huang; Huaguo Liang; Aibin Yan; Xiaoqing Wen (IEEE Trans. Circuits Syst., 2020)

Chip test pattern reordering method using adaptive test to reduce cost for testing of ICs. - Tai Song; Huaguo Liang; Zhengfeng Huang; Tianming Ni; Ying Sun (IEICE Electron. Express, 2021)

Machine learning classification algorithm for VLSI test cost reduction. - Tai Song; Zhengfeng Huang; Aibin Yan (Integr., 2022)

Valid test pattern identification for VLSI adaptive test. - Tai Song; Tianming Ni; Zhengfeng Huang; Jinlei Wan (Integr., 2022)

A double-node-upset completely tolerant CMOS latch design with extremely low cost for high-performance applications. - Aibin Yan; Kuikui Qian; Tai Song; Zhengfeng Huang; Tianming Ni; Yu Chen; Xiaoqing Wen (Integr., 2022)

Low-Power Anti-Glitch Double-Edge Triggered Flip-Flop Based on Robust C-Elements. - Zhengfeng Huang; Wanshu Zhong; Lanxi Duan; Yue Zhang; Huaguo Liang; Jianan Wang; Tai Song; Yingchun Lu (J. Circuits Syst. Comput., 2022)

VLSI test through an improved LDA classification algorithm for test cost reduction. - Liang Huang; Tai Song (Microelectron. J., 2022)

RLDA: Valid test pattern identification by machine learning classification method for VLSI test. - Tai Song; Zhengfeng Huang; Xiaohui Guo (Microelectron. J., 2022)

Linear regression combined KNN algorithm to identify latent defects for imbalance data of ICs. - Liang Huang; Tai Song; Tiezhen Jiang (Microelectron. J., 2023)

Cost-Effective Path Delay Defect Testing Using Voltage/Temperature Analysis Based on Pattern Permutation. - Tai Song; Zhengfeng Huang; Xiaohui Guo; Krstic Milos (J. Electron. Test., 2023)

Overhead Optimized and Quadruple-Node-Upset Self-Recoverable Latch Design Based on Looped C-Element Matrix. - Zhengfeng Huang; Dongxing Ma; Runwu Ji; Huaguo Liang; Aibin Yan; Tai Song; Tianming Ni (IEEE Trans. Aerosp. Electron. Syst., 2023)

Hardened latch designs based on the characteristic of transistor for mitigating multiple-node-upsets in harsh radiation environments. - Hui Xu; Chaoming Liu; Ruijun Ma; Tai Song; Zhengfeng Huang; Jun Wang; Xuewei Qin; Yu Xia (Microelectron. J., 2024)

Designs of High-Speed Triple-Node-Upset Hardened Latch Based on Dual-Modular-Redundancy. - Zhengfeng Huang; Yan Zhang; Lei Ai; Huaguo Liang; Tianming Ni; Tai Song; Aibin Yan (J. Circuits Syst. Comput., 2024)

Test Cost Reduction for VLSI Adaptive Test With K-Nearest Neighbor Classification Algorithm. - Tai Song; Zhengfeng Huang; Li Zhang 083; Qi Hong; Zhao Yang; Milos Krstic (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Low-Cost Quadruple-Node-Upset Self-Recoverable Latch Based on Cross-Interlocking. - Zhengfeng Huang; Lei Ai; Xinyu Jiang; Xiaolei Wang; Yingchun Lu; Jun Pan; Tai Song; Xiaoqing Wen; Aibin Yan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)