Effective Error Diagnosis for RTL Designs in HDLs. - Tai-Ying Jiang; Chien-Nan Jimmy Liu; Jing-Yang Jou (Asian Test Symposium, 2002)

An efficient logic extraction algorithm using partitioning and circuit encoding. - Lily Huang; Tai-Ying Jiang; Jing-Yang Jou; Heng-Liang Huang (ISCAS (5), 2004)

An observability measure to enhance statement coverage metric for proper evaluation of verification completeness. - Tai-Ying Jiang; Chien-Nan Jimmy Liu; Jing-Yang Jou (ASP-DAC, 2005)

Estimating likelihood of correctness for error candidates to assist debugging faulty HDL designs. - Tai-Ying Jiang; Chien-Nan Jimmy Liu; Jing-Yang Jou (ISCAS (6), 2005)

Observability Analysis on HDL Descriptions for Effective Functional Validation. - Tai-Ying Jiang; Chien-Nan Jimmy Liu; Jing-Yang Jou (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Accurate Rank Ordering of Error Candidates for Efficient HDL Design Debugging. - Tai-Ying Jiang; Chien-Nan Jimmy Liu; Jing-Yang Jou (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)