Cell Library Development Methodology for Throughput Enhancement of Electron Beam Direct-Write Lithography Systems. - Makoto Sugihara; Taiga Takata; Kenta Nakamura; Ryoichi Inanami; Hiroaki Hayashi; Katsumi Kishimoto; Tetsuya Hasebe; Yukihiro Kawano; Yusuke Matsunaga; Kazuaki J. Murakami; Katsuya Okumura (SoC, 2005)

A character size optimization technique for throughput enhancement of character projection lithography. - Makoto Sugihara; Taiga Takata; Kenta Nakamura; Ryoichi Inanami; Hiroaki Hayashi; Katsumi Kishimoto; Tetsuya Hasebe; Yukihiro Kawano; Yusuke Matsunaga; Kazuaki J. Murakami; Katsuya Okumura (ISCAS, 2006)

Cell Library Development Methodology for Throughput Enhancement of Character Projection Equipment. - Makoto Sugihara; Taiga Takata; Kenta Nakamura; Ryoichi Inanami; Hiroaki Hayashi; Katsumi Kishimoto; Tetsuya Hasebe; Yukihiro Kawano; Yusuke Matsunaga; Kazuaki J. Murakami; Katsuya Okumura (IEICE Trans. Electron., 2006)

Area recovery under depth constraint by Cut Substitution for technology mapping for LUT-based FPGAs. - Taiga Takata; Yusuke Matsunaga (ASP-DAC, 2008)

An efficient cut enumeration for depth-optimum technology mapping for LUT-based FPGAs. - Taiga Takata; Yusuke Matsunaga (ACM Great Lakes Symposium on VLSI, 2009)

Efficient Cut Enumeration Heuristics for Depth-Optimum Technology Mapping for LUT-Based FPGAs. - Taiga Takata; Yusuke Matsunaga (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

Area Recovery under Depth Constraint for Technology Mapping for LUT-based FPGAs. - Taiga Takata; Yusuke Matsunaga (IPSJ Trans. Syst. LSI Des. Methodol., 2009)

A heuristic algorithm for LUT-based FPGA technology mapping using the lower bound for DAG covering problem (abstract only). - Taiga Takata; Yusuke Matsunaga (FPGA, 2010)

Multiple-bit-upset and single-bit-upset resilient 8T SRAM bitcell layout with divided wordline structure. - Shusuke Yoshimoto; Takuro Amashita; D. Kozuwa; Taiga Takata; Masayoshi Yoshimura; Yusuke Matsunaga; Hiroto Yasuura; Hiroshi Kawaguchi 001; Masahiko Yoshimoto (IOLTS, 2011)

A Robust Algorithm for Pessimistic Analysis of Logic Masking Effects in Combinational Circuits. - Taiga Takata; Yusuke Matsunaga (IPSJ Trans. Syst. LSI Des. Methodol., 2012)

Efficient Fault Simulation Algorithms for Analyzing Soft Error Propagation in Sequential Circuits. - Taiga Takata; Masayoshi Yoshimura; Yusuke Matsunaga (IPSJ Trans. Syst. LSI Des. Methodol., 2013)