Full-chip TSV-to-TSV coupling analysis and optimization in 3D IC. - Chang Liu 034; Taigon Song; Jonghyun Cho; Joohee Kim; Joungho Kim; Sung Kyu Lim (DAC, 2011)

Signal integrity analysis and optimization for 3D ICs. - Chang Liu 034; Taigon Song; Sung Kyu Lim (ISQED, 2011)

Analysis of TSV-to-TSV coupling with high-impedance termination in 3D ICs. - Taigon Song; Chang Liu 034; Dae Hyun Kim 004; Sung Kyu Lim; Jonghyun Cho; Joohee Kim; Junso Pak; Seungyoung Ahn; Joungho Kim; Kihyun Yoon (ISQED, 2011)

3D-MAPS: 3D Massively parallel processor with stacked memory. - Dae Hyun Kim 004; Krit Athikulwongse; Michael B. Healy; Mohammad M. Hossain; Moongon Jung; Ilya Khorosh; Gokul Kumar; Young-Joon Lee; Dean L. Lewis; Tzu-Wei Lin; Chang Liu 034; Shreepad Panth; et al. (ISSCC, 2012)

How to reduce power in 3D IC designs: A case study with OpenSPARC T2 core. - Moongon Jung; Taigon Song; Yang Wan; Young-Joon Lee; Debabrata Mohapatra; Hong Wang; Greg Taylor; Devang Jariwala; Vijay Pitchumani; Patrick Morrow; Clair Webb; Paul Fischer; et al. (CICC, 2013)

Full-chip multiple TSV-to-TSV coupling extraction and optimization in 3D ICs. - Taigon Song; Chang Liu 034; Yarui Peng; Sung Kyu Lim (DAC, 2013)

On accurate full-chip extraction and optimization of TSV-to-TSV coupling elements in 3D ICs. - Yarui Peng; Taigon Song; Dusan Petranovic; Sung Kyu Lim (ICCAD, 2013)

On Enhancing Power Benefits in 3D ICs: Block Folding and Bonding Styles Perspective. - Moongon Jung; Taigon Song; Yang Wan; Yarui Peng; Sung Kyu Lim (DAC, 2014)

Silicon Effect-Aware Full-Chip Extraction and Mitigation of TSV-to-TSV Coupling. - Yarui Peng; Taigon Song; Dusan Petranovic; Sung Kyu Lim (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Full-chip Inter-die Parasitic Extraction in Face-to-Face-Bonded 3D ICs. - Yarui Peng; Taigon Song; Dusan Petranovic; Sung Kyu Lim (ICCAD, 2015)

Three-Tier 3D ICs for More Power Reduction: Strategies in CAD, Design, and Bonding Selection. - Taigon Song; Shreepad Panth; Yoo-Jin Chae; Sung Kyu Lim (ICCAD, 2015)

Die-to-Die Parasitic Extraction Targeting Face-to-Face Bonded 3D ICs. - Taigon Song; Sung Kyu Lim (J. Inform. and Commun. Convergence Engineering, 2015)

Full-Chip Power/Performance Benefits of Carbon Nanotube-Based Circuits. - Taigon Song; Sung Kyu Lim (J. Inform. and Commun. Convergence Engineering, 2015)

Design and Analysis of 3D-MAPS (3D Massively Parallel Processor with Stacked Memory). - Daehyun Kim 004; Krit Athikulwongse; Michael B. Healy; Mohammad M. Hossain; Moongon Jung; Ilya Khorosh; Gokul Kumar; Young-Joon Lee; Dean L. Lewis; Tzu-Wei Lin; Chang Liu 034; Shreepad Panth; et al. (IEEE Trans. Computers, 2015)

More Power Reduction With 3-Tier Logic-on-Logic 3-D ICs. - Taigon Song; Shreepad Panth; Yoo-Jin Chae; Sung Kyu Lim (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

Full-Chip Signal Integrity Analysis and Optimization of 3-D ICs. - Taigon Song; Chang Liu 034; Yarui Peng; Sung Kyu Lim (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Transistor-level monolithic 3D standard cell layout optimization for full-chip static power integrity. - Bon Woong Ku; Taigon Song; Arthur Nieuwoudt; Sung Kyu Lim (ISLPED, 2017)

Design Methodologies for Low-Power 3-D ICs With Advanced Tier Partitioning. - Moongon Jung; Taigon Song; Yarui Peng; Sung Kyu Lim (IEEE Trans. Very Large Scale Integr. Syst., 2017)

A Prediction Scheme in Spiking Neural Network (SNN) Hardware for Ultra-low Power Consumption. - Jeonggyu Yang; Taigon Song (ISOCC, 2020)

Many-Tier Vertical GAAFET (V-FET) for Ultra-Miniaturized Standard Cell Designs Beyond 5 nm. - Taigon Song (IEEE Access, 2020)

NS3K: A 3nm Nanosheet FET Library for VLSI Prediction in Advanced Nodes. - Taehak Kim; Jaehoon Jeong; Seungmin Woo; Jeonggyu Yang; Hyunwoo Kim; Ahyeon Nam; Changdong Lee; Jinmin Seo; Minji Kim 008; Siwon Ryu; Yoonju Oh; Taigon Song (ISCAS, 2021)

An Optimal Design Methodology of Ternary Logic in Iso-device Ternary CMOS. - JongHyun Ko; KwanWoo Park; Suhyeong Yong; TaeGam Jeong; Taehak Kim; Taigon Song (ISMVL, 2021)

A Practical Implementation of the Ternary Logic Using Memristors and MOSFETs. - Jeonggyu Yang; Hyundong Lee; Jaehoon Jeong; Taehak Kim; Sin-Hyung Lee; Taigon Song (ISMVL, 2021)

An Optimized Standard Cell Design Methodology Targeting Low Parasitics and Small Area for Complementary FETs (CFETs). - Eun-Bin Park; Taigon Song (ISOCC, 2021)

A Study on Optimizing Pin Accessibility of Standard Cells in the Post-3 nm Node. - Jaehoon Jeong; JongHyun Ko; Taigon Song (ISLPED, 2022)

A Convenient Implementation of the Ternary Logic: Using Anti-Ambipolar Transistors and PMOS Based on Printed Carbon Nanotubes. - Jongbeom Kim; Yeji Kim; Hyundong Lee; Jihyeong Yun; Hyeseung Jang; Huijeen Jin; Juhee Park; Bongjun Kim; Taigon Song (ISMVL, 2022)

Ternary Competitive to Binary: A Novel Implementation of Ternary Logic Using Depletion-mode and Conventional MOSFETs. - Hyundong Lee; Hyeseung Jang; Jihyeong Yun; Huijeen Jin; Jongbeom Kim; Yeji Kim; Taigon Song (ISMVL, 2022)

A Novel Processing Unit and Architecture for Process-In Memory (PIM) in NAND Flash Memory. - Hyunwoo Kim; Seungwon Baek; Jaehong Song; Taigon Song (ISOCC, 2022)

Circuit-Level Exploration of Ternary Logic Using Memristors and MOSFETs. - Jeonggyu Yang; Hyundong Lee; Jaehoon Jeong; Taehak Kim; Sin-Hyung Lee; Taigon Song (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

High-throughput PIM (Processing in-Memory) for DRAM using Bank-level Pipelined Architecture. - Hyunsoo Lee; Hyundong Lee; Minseung Shin; Gyuri Shin; Sumin Jeon; Taigon Song (ISOCC, 2023)

A Compact Q-Learning-Based Standard Cell Layout Compiler for 3nm GAAFET and Beyond. - MinSeung Shin; Jongbeom Kim; Yunjeong Shin; Taigon Song (ISOCC, 2023)

HFGCN: High-speed and Fully-optimized GCN Accelerator. - MinSeok Han; Jiwan Kim; Donggeon Kim; Hyunuk Jeong; Gilho Jung; Myeongwon Oh; Hyundong Lee; Yunjeong Go; HyunWoo Kim; Jongbeom Kim; Taigon Song (ISQED, 2023)

Cache Register Sharing Structure for Channel-level Near-memory Processing in NAND Flash Memory. - Hyunwoo Kim; Hyundong Lee; Jongbeom Kim; Yunjeong Go; Seungwon Baek; Jaehong Song; Junhyeon Kim; Minyoung Jung; Hyodong Kim; Seongju Kim; Taigon Song (ISQED, 2023)

NS3K: A 3-nm Nanosheet FET Standard Cell Library Development and its Impact. - Taehak Kim; Jaehoon Jeong; Seungmin Woo; Jeonggyu Yang; Hyunwoo Kim; Ahyeon Nam; Changdong Lee; Jinmin Seo; Minji Kim 008; Siwon Ryu; Yoonju Oh; Taigon Song (IEEE Trans. Very Large Scale Integr. Syst., 2023)

Complementary FET (CFET) Standard Cell Design for Low Parasitics and Its Impact on VLSI Prediction at 3-nm Process. - Eun-Bin Park; Taigon Song (IEEE Trans. Very Large Scale Integr. Syst., 2023)

Exploration of Ternary Logic Using T-CMOS for Circuit-Level Design. - JongHyun Ko; Jongbeom Kim; TaeGam Jeong; Jaehoon Jeong; Taigon Song (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

T3L: A Practical Implementation of Tri-Transistor Ternary Logic Based on Inkjet-Printed Anti-Ambipolar Transistors and CMOSs of Thin-Film Structure. - Jongbeom Kim; Hyundong Lee; JongHyun Ko; Bongjun Kim; Taigon Song (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Reinforcement Learning-Based Optimization of Back-Side Power Delivery Networks in VLSI Design for IR -Drop Reduction. - Seungmin Woo; Hyunsoo Lee; Yunjeong Shin; MinSeok Han; Yunjeong Go; Jongbeom Kim; Hyundong Lee; Hyunwoo Kim; Taigon Song (DATE, 2024)

FS2K: A Forksheet FET Technology Library and a Study of VLSI Prediction for 2nm and Beyond. - Yunjeong Shin; Daehyeok Park; Dohun Koh; Dongryul Heo; Jieun Park; Hyundong Lee; Jongbeom Kim; Hyunsoo Lee; Taigon Song (ISCAS, 2024)

Design Technology Co-Optimization and Time-Efficient Verification for Enhanced Pin Accessibility in the Post-3-nm Node. - Jaehoon Jeong; Yunjeong Shin; Hyundong Lee; JongHyun Ko; Jongbeom Kim; Taigon Song (IEEE Access, 2024)

Robust Hardware Trojan Detection Method by Unsupervised Learning of Electromagnetic Signals. - Daehyeon Lee; Junghee Lee; Younggiu Jung; Janghyuk Kauh; Taigon Song (IEEE Trans. Very Large Scale Integr. Syst., 2024)

Ternary Toward Binary: Circuit-Level Implementation of Ternary Logic Using Depletion-Mode and Conventional MOSFETs. - Hyundong Lee; Seonghoon Kim; Jongbeom Kim; Jaehoon Jeong; Jeonggyu Yang; Taigon Song (IEEE Access, 2025)

WACA-UNet: Weakness-Aware Channel Attention for Static IR Drop Prediction in Integrated Circuit Design. - Youngmin Seo; Yunhyeong Kwon; Younghun Park; HwiRyong Kim; Seungho Eum; Jinha Kim; Taigon Song; Juho Kim; Unsang Park (CoRR, 2025)