A 40-ns 64-Mb DRAM with 64-b parallel data bus architecture. - Masao Taguchi; Hiroyoshi Tomita; Toshiya Uchida; Yasuhiro Ohnishi; Kimiaki Sato; Taiji Ema; Masaaki Higashitani; Takashi Yabu (IEEE J. Solid State Circuits, 1991)

Low power ARM® Cortex™-M0 CPU and SRAM using Deeply Depleted Channel (DDC) transistors with Vdd scaling and body bias. - Vineet Agrawal; N. Kepler; David Kidd; Gokul Krishnan; Samuel Leshner; T. Bakishev; D. Zhao; P. Ranade; R. Roy; M. Wojko; Lawrence T. Clark; Robert Rogenmoser; et al. (CICC, 2013)

A 55nm Ultra Low Leakage Deeply Depleted Channel technology optimized for energy minimization in subthreshold SRAM and logic. - Harsh N. Patel; Abhishek Roy 002; Farah B. Yahya; Ningxi Liu; Benton H. Calhoun; Kazuyuki Kumeno; Makoto Yasuda; Akihiko Harada; Taiji Ema (ESSCIRC, 2016)