Using Low Pass Filters in Mitigation Techniques against Single-Event Transients in 45nm Technology LSIs. - Taiki Uemura; Ryo Tanabe; Yoshiharu Tosaka; Shigeo Satoh (IOLTS, 2008)

Investigation of multi cell upset in sequential logic and validity of redundancy technique. - Taiki Uemura; Takashi Kato; Hideya Matsuyama; Keiji Takahisa; Mitsuhiro Fukuda; Kichiji Hatanaka (IOLTS, 2011)

A 10th generation 16-core SPARC64 processor for mission-critical UNIX server. - Ryuji Kan; Tomohiro Tanaka; Go Sugizaki; Ryuichi Nishiyama; Sota Sakabayashi; Yoichi Koyanagi; Ryuji Iwatsuki; Kazumi Hayasaka; Taiki Uemura; Gaku Ito; Yoshitomo Ozeki; Hiroyuki Adachi; et al. (ISSCC, 2013)

The 10th Generation 16-Core SPARC64™ Processor for Mission Critical UNIX Server. - Ryuji Kan; Tomohiro Tanaka; Go Sugizaki; Kinya Ishizaka; Ryuichi Nishiyama; Sota Sakabayashi; Yoichi Koyanagi; Ryuji Iwatsuki; Kazumi Hayasaka; Taiki Uemura; Gaku Ito; Yoshitomo Ozeki; et al. (IEEE J. Solid State Circuits, 2014)

Critical charge dependence of correlation of different neutron sources for soft error testing. - Hiroko Mori; Taiki Uemura; Hideya Matsuyama; Shin-ichiro Abe; Yukinobu Watanabe (IRPS, 2015)

Investigation of single event upset and total ionizing dose in FeRAM for medical electronic tag. - Taiki Uemura; Masanori Hashimoto (IRPS, 2015)

Impact of package on neutron induced single event upset in 20 nm SRAM. - Taiki Uemura; Takashi Kato; Hideya Matsuyama; Masanori Hashimoto (IRPS, 2015)

Soft error immune latch design for 20 nm bulk CMOS. - Taiki Uemura; Takashi Kato; Hideya Matsuyama; Masanori Hashimoto (IRPS, 2015)

Investigation of alpha-induced single event transient (SET) in 10 nm FinFET logic circuit. - Taiki Uemura; Soonyoung Lee; Dahye Min; Ihlhwa Moon; Jungman Lim; Seungbae Lee; Hyun-Chul Sagong; Sangwoo Pae (IRPS, 2018)

Reliability of 8Mbit Embedded-STT-MRAM in 28nm FDSOI Technology. - Y. Ji; H. J. Goo; J. Lim; S. B. Lee; S. Lee; Taiki Uemura; J. C. Park; S. I. Han; S. C. Shin; J. H. Lee; Y. J. Song; K. M. Lee; et al. (IRPS, 2019)

SEIFF: Soft Error Immune Flip-Flop for Mitigating Single Event Upset and Single Event Transient in 10 nm FinFET. - Taiki Uemura; Soonyoung Lee; Dahye Min; Ihlhwa Moon; Seungbae Lee; Sangwoo Pae (IRPS, 2019)

Reliability on EUV Interconnect Technology for 7nm and beyond. - Tae-Young Jeong; Miji Lee; Yunkyung Jo; Jinwoo Kim; Min Kim; Myungsoo Yeo; Jinseok Kim 005; Hyunjun Choi; Joosung Kim; Yoojin Jo; Yongsung Ji; Taiki Uemura; et al. (IRPS, 2020)

Reliability of Industrial grade Embedded-STT-MRAM. - Yongsung Ji; Hyunjae Goo; Jungman Lim; Tae-Young Jeong; Taiki Uemura; Gun Rae Kim; Boil Seo; Seungbae Lee; Goeun Park; Jeongmin Jo; Sang-Il Han; Kilho Lee; et al. (IRPS, 2020)

Advanced Self-heating Model and Methodology for Layout Proximity Effect in FinFET Technology. - Hai Jiang 005; Hyun-Chul Sagong; Jinju Kim; Hyewon Shim; Yoohwan Kim; Junekyun Park; Taiki Uemura; Yongsung Ji; Taeyoung Jeong; Dongkyun Kwon; Hwasung Rhee; Sangwoo Pae; et al. (IRPS, 2020)

Early Diagnosis and Prediction of Wafer Quality Using Machine Learning on sub-10nm Logic Technology. - Heung-Kook Ko; Sena Park; Jihyun Ryu; Sung Ryul Kim; Giwon Lee; Dongjoon Lee; Sangwoo Pae; Euncheol Lee; Yongsun Ji; Hai Jiang 005; Taeyoung Jeong; Taiki Uemura; et al. (IRPS, 2020)

Backside Alpha-Irradiation Test in Flip-Chip Package in EUV 7 nm FinFET SRAM. - Taiki Uemura; Byungjin Chung; Jeongmin Jo; Hai Jiang 005; Yongsung Ji; Tae-Young Jeong; Rakesh Ranjan; Seungbae Lee; Hwasung Rhee; Sangwoo Pae; Euncheol Lee; Jaehee Choi; et al. (IRPS, 2020)

Investigating of SER in 28 nm FDSOI-Planar and Comparing with SER in Bulk-FinFET. - Taiki Uemura; Byungjin Chung; Jeongmin Jo; Hai Jiang 005; Yongsung Ji; Tae-Young Jeong; Rakesh Ranjan; Youngin Park; Kiil Hong; Seungbae Lee; Hwasung Rhee; Sangwoo Pae; et al. (IRPS, 2020)

Soft-Error Susceptibility in Flip-Flop in EUV 7 nm Bulk-FinFET Technology. - Taiki Uemura; Byungjin Chung; Jeongmin Jo; Mijoung Kim; Dalhee Lee; Gunrae Kim; Seungbae Lee; Taesjoong Song; Hwasung Rhee; Brandon Lee; Jaehee Choi (IRPS, 2021)

Thermal-Neutron SER Mitigation by Cobalt-Contact in 7 nm Bulk-FinFET Technology. - Taiki Uemura; Byungjin Chung; Jegon Kim; Hyewon Shim; Shin-Young Chung; Brandon Lee; Jaehee Choi; Shota Ohnishi; Ken Machida (IRPS, 2022)

Accelerator-Based Thermal-Neutron Beam by Compact and Low-Cost Moderator for Soft-Error Evaluation in Semiconductor Devices. - Taiki Uemura; Byungjin Chung; Jegon Kim; Hyewon Shim; Shin-Young Chung; Brandon Lee; Jaehee Choi; Shota Ohnishi; Ken Machida (IRPS, 2022)

Machine Learning Based V-ramp VBD Predictive Model Using OCD-measured Fab Parameters for Early Detection of MOL Reliability Risk. - SungMan Rhee; Hyunjin Kim; Sangku Park; Taiki Uemura; Yuchul Hwang; Seungjin Choo; Jinju Kim; Hwasung Rhee; Shin-Young Chung (IRPS, 2023)

Impact of Design and Process on Alpha-Induced SER in 4 nm Bulk-FinFET SRAM. - Taiki Uemura; Byungjin Chung; Shin-Young Chung; Seungbae Lee; Yuchul Hwang; Sangwoo Pae (IRPS, 2023)

Soft-Error Sensitivity in SRAM Manufactured by Bulk Gate-All-Around (GAA) Technology. - Taiki Uemura; Byungjin Chung; Jaehee Choi; Seungbae Lee; Shin-Young Chung; Yuchul Hwang; Sangwoo Pae (IRPS, 2024)

Comprehensive Study of SER in FDSOI-Planar: 28 nm to 18 nm Scaling Effect and Temperature Dependence. - Taiki Uemura; Byungjin Chung; Jaehee Choi; Seungbae Lee; Shin-Young Chung; Yuchul Hwang; Sangwoo Pae (IRPS, 2024)

Reliability Impacts of Tapered Nanosheets and Localized Layout Effects in MBCFETs Fabricated with 2NM Logic Technology Featuring GAA. - Seongkyung Kim; Eunyu Choi; Jinyoung Kim; Junkyo Jeong; Jihun Ryu; Myungsoo Yeo; Taiki Uemura; Shin-Young Chung; Jong-Ho Lee (IRPS, 2025)

Introduction to Voltage-Ramping Wafer Level Electromigration Method and Current Exponent Correction Factor for Co-Capping Metal Lines. - Da Yong Shin; Hyunjun Choi; Joosung Kim; Myungsoo Yeo; Miji Lee; Taiki Uemura; Shin-Young Chung; Jong-Ho Lee (IRPS, 2025)

Cost-Effective Assessment of Neutron-Induced SER Using Single Proton Irradiation Test with Fixed Correlation Factor. - Taiki Uemura; SungSoo Kim; Shinyoung Chung; Jong-Ho Lee (IRPS, 2025)

Comprehensive Study of Thermal Neutron SER in Bulk-Planar, Bulk-FinFET, FDSOI-Planar, and Bulk-GAA Technology, Evaluated at HANARO. - Taiki Uemura; Jongyul Kim 003; Sungsoo Kim; Shinyoung Chung; Jong-Ho Lee (IRPS, 2025)