Transient analysis of large linear dynamic networks on hybrid GPU-multicore platforms. - Xuexin Liu; Sheldon X.-D. Tan; Zao Liu; Hai Wang 002; Tailong Xu (NEWCAS, 2012)

Dynamic thermal management for multi-core microprocessors considering transient thermal effects. - Zao Liu; Tailong Xu; Sheldon X.-D. Tan; Hai Wang 002 (ASP-DAC, 2013)

A wide-range and ultra fast-locking all-digital SAR DLL without harmonic-locking. - Zhikuang Cai; Tailong Xu; Haiyan Sun; Longxing Shi (IEICE Electron. Express, 2013)

Design and implementation of elastic buffer for Universal Serial Bus 3.0. - Hong Chang; Te Peng; Daoming Ke; Tailong Xu; Jian Meng (IEICE Electron. Express, 2016)

A harmonic-free cell-based all-digital delay-locked loop for die-to-die clock synchronization of 3-D IC. - Tailong Xu; Feng Xue; Zhikuang Cai; Xinning Liu; Shuo Meng (ASICON, 2017)

Blockchain Enabled Tracking of Physician Burnout and Stressors During the COVID-19 Pandemic. - Vikram Dhillon; Tailong Xu; Chirag Parikh (Frontiers Blockchain, 2020)

A 600-μm² Ring-VCO-Based Hybrid PLL Using a 30-μW Charge-Sharing Integrator in 28-nm CMOS. - Shiheng Yang; Jun Yin 001; Tailong Xu; Taimo Yi; Pui-In Mak; Qiang Li 021; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A 6-to-7.5-GHz 54-fsrms Jitter Type-II Reference-Sampling PLL Featuring a Gain-Boosting Phase Detector for In-Band Phase-Noise Reduction. - Tailong Xu; Shenke Zhong; Jun Yin 001; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A 16MHz X0 with 17.5μs Startup Time Under 104ppm-ΔF Injection Using Automatic Phase-Error Correction Technique. - Zhikuang Cai; Xin Wang 147; Zixuan Wang; Yunjin Yin; Wenjing Zhang; Tailong Xu; Yufeng Guo (ISSCC, 2023)

On the DC-Settling Process of the Pierce Crystal Oscillator in Start-Up. - Zehao Zhang; Shiheng Yang; Yueduo Liu; Zihao Zhu; Jiahui Lin; Rongxin Bao; Tailong Xu; Zhizhan Yang; Mingkang Zhang; Jiaxin Liu; Xiong Zhou; Jun Yin 001; et al. (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A 6.0-to-6.9GHz 99fsrms-Jitter Type-II Sampling PLL with Automatic Frequency and Phase Calibration Method Achieving 0.62μs Locking Time in 28nm CMOS. - Jian Yang; Tailong Xu; Xi Meng; Zhenghao Li; Jun Yin 001; Pui-In Mak; Rui Paulo Martins; Quan Pan 002 (CICC, 2024)

10.9 A 23.2-to-26GHz Sub-Sampling PLL Achieving 48.3fsrms Jitter, -253.5dB FoMJ, and 0.55μs Locking Time Based on a Function-Reused VCO-Buffer and a Type-I FLL with Rapid Phase Alignment. - Haoran Li; Tailong Xu; Xi Meng; Jun Yin 001; Rui Paulo Martins; Pui-In Mak (ISSCC, 2024)

A 16-MHz Crystal Oscillator With 17.5- μ s Start-Up Time Under 104-ppm- Δ F Injection Using Automatic Phase-Error Correction. - Zixuan Wang; Xin Wang 147; Ka-Meng Lei; Wenjing Zhang; Yunjin Yin; Tailong Xu; Zhikuang Cai; Yufeng Guo; Pui-In Mak (IEEE J. Solid State Circuits, 2024)

A 23.2-to-26-GHz Low-Jitter Fast-Locking Sub-Sampling PLL Based on a Function-Reused VCO-Buffer and a Type-I FLL With Rapid Phase Alignment. - Haoran Li; Tailong Xu; Xi Meng; Jun Yin 001; Rui Paulo Martins; Pui-In Mak (IEEE J. Solid State Circuits, 2024)

Analysis and Design of a Type-II Reference-Sampling PLL Using Gain-Boosting Phase Detector With Sampling Capacitor Reduction. - Tailong Xu; Haoran Li; Xi Meng; Xiangxun Zhan; Yatao Peng; Jun Yin 001; Shiheng Yang; Chao Fan; Zhixiang Huang; Rui Paulo Martins; Pui-In Mak (IEEE Trans. Circuits Syst. II Express Briefs, 2025)

Design and Analysis of a Type-II Sampling PLL With Automatic Frequency and Phase Calibrations Achieving 0.62-μs Locking Time. - Jian Yang; Tailong Xu; Xi Meng; Zhenghao Li; Jun Yin 001; Rui Paulo Martins; Pui-In Mak; Quan Pan 002 (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)