A 1.33Tb 4-bit/Cell 3D-Flash Memory on a 96-Word-Line-Layer Technology. - Noboru Shibata; Kazushige Kanda; Takahiro Shimizu; Jun Nakai; Osamu Nagao; Naoki Kobayashi 004; Makoto Miakashi; Yasushi Nagadomi; Takeshi Nakano; Takahisa Kawabe; Taira Shibuya; Mario Sako; et al. (ISSCC, 2019)

A 1.33-Tb 4-Bit/Cell 3-D Flash Memory on a 96-Word-Line-Layer Technology. - Noboru Shibata; Takahisa Kawabe; Taira Shibuya; Mario Sako; Kosuke Yanagidaira; Toshifumi Hashimoto; Hiroki Date; Manabu Sato; Tomoki Nakagawa; Junji Musha; Takatoshi Minamoto; Kazushige Kanda; et al. (IEEE J. Solid State Circuits, 2020)

7-Bit/2Cell (X3.5), 9-Bit/2Cell (X4.5) NAND Flash Memory: Half Bit technology. - Noboru Shibata; Hironori Uchikawa; Taira Shibuya; Kenri Nakai; Kosuke Yanagidaira; Hirofumi Inoue (IMW, 2023)

Novel Multi-Level Coding and Architecture Enabling Fast Random Access for Flash Memory. - Noboru Shibata; Hironori Uchikawa; Taira Shibuya; Hirofumi Inoue (IMW, 2024)

Fast Readable Multi-Cell Coding for Flash Memory. - Hironori Uchikawa; Noboru Shibata; Taira Shibuya (ISIT, 2024)