ECR: a low complexity generalized error cancellation rewiring scheme. - Xiaoqing Yang; Tak-Kei Lam; Yu-Liang Wu (DAC, 2010)

Logic synthesis for low power using clock gating and rewiring. - Tak-Kei Lam; Steve Yang; Wai-Chung Tang; Yu-Liang Wu (ACM Great Lakes Symposium on VLSI, 2010)

On applying erroneous clock gating conditions to further cut down power. - Tak-Kei Lam; Xiaoqing Yang; Wai-Chung Tang; Yu-Liang Wu (ASP-DAC, 2011)

On Structural Analysis and Efficiency for Graph-Based Rewiring Techniques. - Fu-Shing Chim; Tak-Kei Lam; Yu-Liang Wu; Hongbing Fan (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011)

Almost every wire is removable: A modeling and solution for removing any circuit wire. - Xiaoqing Yang; Tak-Kei Lam; Wai-Chung Tang; Yu-Liang Wu (DATE, 2012)

ECR: A Powerful and Low-Complexity Error Cancellation Rewiring Scheme. - Tak-Kei Lam; Wai-Chung Tang; Xiaoqing Yang; Yu-Liang Wu (ACM Trans. Design Autom. Electr. Syst., 2012)

On macro-fault: a new fault model, its implications on fault tolerance and manufacturing yield. - Tak-Kei Lam; Xing Wei; Wen-Ben Jone; Yi Diao; Yu-Liang Wu (ACM Great Lakes Symposium on VLSI, 2014)

Delete and Correct (DaC): An Atomic Logic Operation for Removing Any Unwanted Wire. - Xing Wei; Tak-Kei Lam; Xiaoqing Yang; Wai-Chung Tang; Yi Diao; Yu-Liang Wu (VLSID, 2014)

A coupling area reduction technique applying ODC shifting. - Yi Diao; Tak-Kei Lam; Xing Wei; Yu-Liang Wu (DATE, 2015)

A universal macro block mapping scheme for arithmetic circuits. - Xing Wei; Yi Diao; Tak-Kei Lam; Yu-Liang Wu (DATE, 2015)

Coupling reverse engineering and SAT to tackle NP-complete arithmetic circuitry verification in ∼O(# of gates). - Yi Diao; Xing Wei; Tak-Kei Lam; Yu-Liang Wu (ASP-DAC, 2016)