On-chip inductance modeling and RLC extraction of VLSI interconnects for circuit simulation. - Xiaoning Qi; Gaofeng Wang; Zhiping Yu; Robert W. Dutton; Tak Young; Norman Chang (CICC, 2000)

When bad things happen to good chips (panel session). - N. S. Nagaraj; Andrzej J. Strojwas; Sani R. Nassif; Ray Hokinson; Tak Young; Wonjae L. Kang; David Overhauser; Sung-Mo Kang (DAC, 2000)

Min/max On-Chip Inductance Models and Delay Metrics. - Yi-Chang Lu; Mustafa Celik; Tak Young; Lawrence T. Pileggi (DAC, 2001)

On-Chip Inductance Extraction and Modeling. - Tak Young (ISQED, 2001)