Clock tree embedding for 3D ICs. - Tak-Yung Kim; Taewhan Kim 001 (ASP-DAC, 2010)

Clock tree synthesis with pre-bond testability for 3D stacked IC designs. - Tak-Yung Kim; Taewhan Kim 001 (DAC, 2010)

Bounded skew clock routing for 3D stacked IC designs: Enabling trade-offs between power and clock skew. - Tak-Yung Kim; Taewhan Kim 001 (Green Computing Conference, 2010)

Clock Tree synthesis for TSV-based 3D IC designs. - Tak-Yung Kim; Taewhan Kim 001 (ACM Trans. Design Autom. Electr. Syst., 2011)

Resource Allocation and Design Techniques of Prebond Testable 3-D Clock Tree. - Tak-Yung Kim; Taewhan Kim 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)