Over-the-top Si Interposer Embedding Backside Buried Metal PDN to Reduce Power Supply Impedance of Large Scale Digital ICs. - Takuji Miki; Makoto Nagata; Akihiro Tsukioka; Noriyuki Miura; Takaaki Okidono; Yuuki Araga; Naoya Watanabe; Haruo Shimamoto; Katsuya Kikuchi (3DIC, 2019)

Si-Backside Protection Circuits Against Physical Security Attacks on Flip-Chip Devices. - Takuji Miki; Makoto Nagata; Hiroki Sonoda; Noriyuki Miura; Takaaki Okidono; Yuuki Araga; Naoya Watanabe; Haruo Shimamoto; Katsuya Kikuchi (IEEE J. Solid State Circuits, 2020)

A Triturated Sensing System. - Noriyuki Miura; Kotaro Naruse; Jun Shiomi; Yoshihiro Midoh; Tetsuya Hirose; Takaaki Okidono; Takuji Miki; Makoto Nagata (ISSCC, 2023)

Thermal Flow Simuation and Measurements of 3D Si Chip Stacks with TSVs. - Shuhei Yokota; Rikuu Hasegawa; Kazuki Monta; Takaaki Okidono; Takuji Miki; Makoto Nagata (3DIC, 2024)