Test circuits for substrate noise evaluation in CMOS digital ICs. - Makoto Nagata; Takafumi Ohmoto; Jin Nagai; Takashi Morie; Atsushi Iwata (ASP-DAC, 2001)

Chip-Level Substrate Noise Analysis with Network Reduction by Fundamental Matrix Computation. - Yoshitaka Murasaka; Makoto Nagata; Takafumi Ohmoto; Takashi Morie; Atsushi Iwata (ISQED, 2001)

A substrate noise analysis methodology for large-scale mixed-signal ICs. - Wen Kung Chu; Nishath K. Verghese; Heayn-Jun Chol; Kenji Shimazaki; Hiroyuki Tsujikawa; Shouzou Hirano; Shirou Doushoh; Makoto Nagata; Atsushi Iwata; Takafumi Ohmoto (CICC, 2003)

Background Calibration Techniques for Low-Power and High-Speed Data Conversion. - Atsushi Iwata; Yoshitaka Murasaka; Tomoaki Maeda; Takafumi Ohmoto (IEICE Trans. Electron., 2011)