Gate Model Networks for Minimization of Multiple-Valued Logic Functions. - Yutaka Hata; Takahiro Hozumi; Kazuharu Yamato (ISMVL, 1993)

Multiple-Valued Logic Design Using Multiple-Valued EXOR. - Takahiro Hozumi; Naotake Kamiura; Yutaka Hata; Kazuharu Yamato (ISMVL, 1995)

Design of Fuzzy Plas Using Fuzzy Decision Diagrams. - Yutaka Hata; Koji Takiguchi; Takahiro Hozumi; Kazuharu Yamato (Intell. Autom. Soft Comput., 1995)

Multiple-Valued Logic Minimization by Genetic Algorithms. - Yutaka Hata; Kiyoshi Hayase; Takahiro Hozumi; Naotake Kamiura; Kazuharu Yamato (ISMVL, 1997)

On Low Cost Realization of Multiple-Valued Logic Functions. - Takahiro Hozumi; Osamu Kakusho; Yutaka Hata (ISMVL, 1998)

The Output Permutation for the Multiple-Valued Logic Minimization with Universal Literals. - Takahiro Hozumi; Osamu Kakusho; Yutaka Hata (ISMVL, 1999)

An Evolutionary Computing Approach to Multilevel Logic Synthesis Using Various Logic Operations. - Takahiro Hozumi; Osamu Kakusho; Kazuharu Yamato (ISMVL, 2000)