An ultra-high-density high-speed loadless four-transistor SRAM macro with a dual-layered twisted bit-line and a triple-well shield. - Kenji Noda; Koujirou Matsui; Shinya Ito; Sadaaki Masuoka; Hiroyuki Kawamoto; Nobuyuki Ikezawa; Koichi Takeda 001; Yoshiharu Aimoto; Naoto Nakamura; Hideo Toyoshima; Takahiro Iwasaki; Tadahiko Horiuchi (CICC, 2000)

A 16-Mb 400-MHz loadless CMOS four-transistor SRAM macro. - Koichi Takeda 001; Yoshiharu Aimoto; Noritsugu Nakamura; Hideo Toyoshima; Takahiro Iwasaki; Kenji Noda; Koujirou Matsui; Shinya Itoh; Sadaaki Masuoka; Tadahiko Horiuchi; Atsushi Nakagawa; Kenju Shimogawa; et al. (IEEE J. Solid State Circuits, 2000)

An ultrahigh-density high-speed loadless four-transistor SRAM macro with twisted bitline architecture and triple-well shield. - Kenji Noda; Koichi Takeda 001; Koujirou Matsui; Shinya Ito; Sadaaki Masuoka; Hideaki Kawamoto; Nobuyuki Ikezawa; Yoshiharu Aimoto; Noritsugu Nakamura; Takahiro Iwasaki; Hideo Toyoshima; Tadahiko Horiuchi (IEEE J. Solid State Circuits, 2001)

Application of Error Diagnosis Technique to Incremental Synthesis. - Hiroshi Inoue; Takahiro Iwasaki; Toshifumi Sugane; Masahiro Numa; Keisuke Yamamoto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)