Headfirst sliding routing: A time-based routing scheme for bus-NoC hybrid 3-D architecture. - Takahiro Kagami; Hiroki Matsutani; Michihiro Koibuchi; Hideharu Amano (NOCS, 2013)

A low power NoC router using the marching memory through type. - Ryota Yasudo; Takahiro Kagami; Hideharu Amano; Yasunobu Nakase; Masashi Watanabe; Tsukasa Oishi; Toru Shimizu; Tadao Nakamura (COOL Chips, 2014)

Low-latency wireless 3D NoCs via randomized shortcut chips. - Hiroki Matsutani; Michihiro Koibuchi; Ikki Fujiwara; Takahiro Kagami; Yasuhiro Take; Tadahiro Kuroda; Paul Bogdan; Radu Marculescu; Hideharu Amano (DATE, 2014)

Design of a low power NoC router using Marching Memory Through type. - Ryota Yasudo; Takahiro Kagami; Hideharu Amano; Yasunobu Nakase; Masashi Watanabe; Tsukasa Oishi; Toru Shimizu; Tadao Nakamura (NOCS, 2014)

Efficient 3-D Bus Architectures for Inductive-Coupling ThruChip Interfaces. - Takahiro Kagami; Hiroki Matsutani; Michihiro Koibuchi; Yasuhiro Take; Tadahiro Kuroda; Hideharu Amano (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Automatic Power Saving Method by Energy Aware Job Scheduler. - Hiroaki Imade; Takahiro Kagami; Tomohiro Otawa; Kouichi Hirai; Yoshio Sakaguchi; Naoyuki Fujita (CLUSTER, 2019)